III-V MOSFETs: Scaling Laws, Scaling Limits, Fabrication Processes M. J. W. Rodwell a , U. Singisetti a , M.Wistey a,b , G. J. Burek a , A. Carter a , A. Baraskar a , J. Law a , B. J. Thibeault a , Eun Ji Kim c , B. Shin c , Yong-ju Lee d , S. Steiger e , S. Lee e , H. Ryu e , Y. Tan e , G. Hegde e , L. Wang f , E. Chagarov f , A.C. Gossard a , W. Frensley g , A. Kummel f , C. Palmstrøm a , Paul C McIntyre c , T. Boykin h , G. Klimek e P. Asbeck f , a Departments of ECE and Materials, University of California, Santa Barbara, b Now at the University of Notre Dame c Materials Science and Engineering Department, Stanford University, d Intel Corporation e Purdue University, f Departments of ECE and Materials, University of California, San Diego g University of Texas, Dallas, h University of Alabama, Huntsville Abstract—III-V FETs are in development for both THz and VLSI applications. In VLSI, high drive currents are sought at low gate drive voltages, while in THz circuits, high cutoff frequencies are required. In both cases, source and drain access resistivities must be decreased, and transconductance and drain current per unit gate width must be increased by reducing the gate dielectric thickness, reducing the inversion layer depth, and increasing the channel 2-DEG density of states. We here describe both nm self-aligned fabrication processes and channel designs to address these scaling limits. I. INTRODUCTION III-V transistors of ~10 to 100 nm lithographic dimensions are being developed both for sub-mm-wave (0.3--3 THz) applications and for use in large-scale digital integrated circuits. Both applications demand improved transistor characteristics; both applications demand significant changes in the design and fabrication of the channel, of the source/drain access regions, and of the gate dielectric. For application in VLSI, FET leakage currents must be low and drain drive current densities must be high despite low supply voltages. High intrinsic transconductance and low source / drain access resistivities are therefore required. For application in THz ICs, high current-gain (  f ) and power-gain ( max f ) cutoff frequencies are required. With present InGaAs HEMTs,  f is limited by parasitic capacitance charging times which are only reduced by increasing the FET transconductance per unit gate width. As with the VLSI application, the drive current and transconductance must be increased and the source access resistance reduced. THz InGaAs HEMTs and InGaAs MOSFETs thus face several similar design challenges. To increase the transconductance of both HEMTs and MOSFETs, the gate barrier must be thinned, which increases gate leakage. In VLSI application, gate leakage must be very small, and an MOS structure with a wide-gap (insulating) gate dielectric is required. Even for HEMTs used in THz ICs, the wide-gap gate barrier semiconductor layer has been thinned to the point where gate leakage reduces microwave power gain; better barriers are needed. In both devices high transconductance implies both high carrier velocities and high carrier densities in the 2-dimensional electron gas. Semiconductors with low carrier effective mass provide high carrier velocities yet low 2-D densities of states hence low carrier densities, high effective mass provides low velocities yet high carrier densities. [1] This limitation must somehow be addressed. Both devices need low access resistances. Both devices need thin channels both for high transconductance and for low output conductance. Design challenges with THz InGaAs HEMTs and InGaAs MOSFETs also differ in key aspects. Unlike THz HEMTs, where overall device dimensions can be much larger than the gate length, in VLSI the device packing density must be high hence all device dimensions must be small. In particular, in VLSI the source/drain contacts must have dimensions comparable to the gate length, placing greater demands on low- resistivity source/drain contacts. Similarly, while in THz HEMTs the N+ drain can have a large offset from the gate to reduce drain electrostatic coupling and consequently output conductance, in MOSFETs for VLSI both density and logic design requirements force the N+ drain region to be placed adjacent to or under the gate. Electrostatic design and vertical scaling of the VLSI device is therefore more demanding. We describe below our efforts to develop III-V MOSFETs for VLSI. Although III-V MOS gate dielectrics [2, 3] remain an area of intense development, we focus here on device design and on development of process flows for fabrication of nm devices. Since their low 2-dimensional density of states makes III-V channel materials uncompetitive for application in nm FETs, we also discuss modified III-V channel designs which address this limitation. II. FET SCALING LAWS First consider FET scaling laws (Table 1) [4] . To increase bandwidth  :1, capacitances and transit delays must be reduced  :1 while maintaining constant voltages, currents, and resistances. In InGaAs FETs with g L ~35 nm, the gate-source g f gs W C   , and gate- drain g gd W C   fringing capacitances are a substantial fraction of the total capacitance, and consequently limit  f . f gs C , and gd C are only weakly dependent on lateral