IJSRD - International Journal for Scientific Research & Development| Vol. 3, Issue 06, 2015 | ISSN (online): 2321-0613 All rights reserved by www.ijsrd.com 1352 Design of High Speed All Digital Phase Lock Loop for FM Application Sujata Pujari 1 Nayina Ramapur 2 Dr.T. C.Thanuja 3 1,2 M.Tech. Student 3 Professor 1,2,3 Department of VLSI Design and Embedded System 1,2,3 VTU Belgaum Abstract— All Digital Phase Lock Loop (ADPLL) is contributing in advancement in digital communication and control system since 1980. In this paper “High speed ADPLL for FM application” is proposed. The ADPLL is designed using phase detector, digital loop filter and increment-decrement counter. Here the speed of ADPLL is increased by using novel multiplexer based increment – decrement counter. The ADPLL using these blocks are simulated by using Xilinx 14.5. It is observed that the delay of proposed ADPLL is less compare to existing ADPLL [1]. Further, the proposed ADPLL is used to generate FM modulation by using interpolator method. Key words: PLL, ADPLL, FM Modulation I. INTRODUCTION The phase lock loop (PLL)[2] is a feedback control system. The primary functionality of a PLL is to compare the phase and frequency of the input signal with that of feedback signal, then adjust the feedback signal till the phase error becomes completely zero. For communication systems and many modern electronics and electrical system, the PLL act as an important part. In the communication field, PLL is used to generate and modulate the signal. The modulation and demodulation of signal is mainly used in the receiver system hence it is implied that PLL is inevitable for the receivers. The PLL has much more applications like frequency synthesis, clock recovery and clock generation in communications and networking system. The analog PLL has many disadvantages like, it occupies more implementation area, more delay, and also it is easily susceptible to noise due to analog component in the design. So there is a necessity of PLL, to be designed in digital, so that it is used in digital communication system. In order to overcome the disadvantages of the analog PLL digital phase lock loop are proposed. Due to the digital design, it has minimum area, minimum delay and low power consumption. Most of the researchers have conducted research on the PLL[3,4] to realize higher speed minimum chip area and minimum phase noise PLLs are classified into four types they are i). Linear PLL or analog PLL ii).Digital Phase Locked Loop iii).All Digital Phase Locked Loop iv). Software PLL(SPLL). The enhanced phase locked loop[5] was designed by using the combination of a 4-state PFD (phase and frequency detector) with a latching circuit. In this method lock time is reduced by using initial bias circuit. After the PLL, the early effort on the digital PLL was concentrated on replacing analog component partially with digital component. The author Westlake [6] was the first person worked in this direction in year of 1960. He was used a sample and hold circuit to take the advantage of digital voltage controlled oscillator The ADPLL design based on the double edge triggered D flip flop [7] was designed. This type of ADPLL resolves the key issues like by-direction zero crossing and phase detection. The whole design is coded by using HDL and implemented on FPGA. The synthesis report shows that the speed of whole loop is increased by twice compared to conventional PLL. Due to the use of DETDFF(double edge triggered D flip flop) there is reduction of 33% power dissipation. The survey of many papers, illustrated. some limitation in PLL like delay, area and power. In this paper a high speed ADPLL for FM application is designed. Here the speed is increased by using a novel multiplexer based increment-decrement counter. The paper is divided in the several sections as follows: Section II provides the ADPLL design and describes all the building blocks of the ADPLL. Section III describes the simulation result of ADPLL design. Section IV provides the Conclusion and future scope of the paper. II. PROPOSED METHODOLOGY A. Design of ADPLL The ADPLL resembles the conventional PLL in structure but all the components and intermediate signals are digital in nature. The figures1shows the basic block diagram of ADPLL. Fig 1: Block diagram of ADPLL The basic operation of an ADPLL [9] mainly depends on three important building blocks they are namely a digital phase detector, digital loop filter, and digital increment and decrement counter as a controlled oscillator. The brief discussion of each of these blocks are given in the subsequent sections. 1) Phase Detector The main building block of ADPLL is a phase detector, here the phase detector is considered as a simple XOR gate. Based on the inputs of the phase detector the error signal is produced at the output side of phase detector. The inputs to the phase detector are input reference clock signal and the output of the divide by B- counter. The output of phase detector is given as input to digital loop filter