Impact of Cache Power Reduction Techniques in Multi-core Processor using Network On-Chip Paradigm Abinash Roy, Sandhya Jeevan ϒ , Jingye Xu and Masud H. Chowdhury Department of Electrical and Computer Engineering, University of Illinois at Chicago Chicago, IL 60607, USA aroy5@uic.edu, sjeeva2@uic.edu, jxu6@uic.edu, masudh@uic.edu Abstract—Caches which are an essential part of memory systems consume a significant amount of power. A number of techniques have been proposed in the literature to reduce power consumption in cache modules. In this paper a survey of various widely used circuit and architecture level techniques for cache power management system is presented to investigate an effective approach for multi-core system-on-chip employing network-on-chip design paradigm. Specific focus has been given on the gated-VDD and drowsy cache schemes. Instead of offering a new cache power management scheme we performed a comparative analysis of the impacts of available techniques on the performance and leakage power reduction in multi-core environment. Based on the analysis, several promising aspects and associated challenges have been projected. I. INTRODUCTION Higher performance requirement in successive technologies leads to dramatic increase of the number and speed of circuit components in a microprocessor. As a result, both dynamic and leakage powers have been increasing drastically. However, with the aggressive scaling of transistor dimensions leakage power has become dominant over dynamic power. Leakage power is a problem for all micro- processor and micro-controller circuit components, but it is particularly an important problem in caches where enormous numbers of potentially high leakage memory cells are integrated in a confined area. Since caches account for a large portion of on-chip transistors, it is imperative that power reduction in cache blocks/cores is one of the major design targets. Among the proposed schemes, most of them deal with completely turning off cache lines [5] putting them in a drowsy mode [6]. These schemes have been tested and proved to be successful with certain trade-offs in single processors. Moving into the billion transistor era some of the current and emerging chip design architectures or platforms tend to adopt network-on-a-chip (NOC) [1] and multi-core approach for high design productivity and performance. As the cache size and number increases in these new platforms, leakage contributes even higher percentage of the total power. In this paper the effectiveness of the low power cache techniques used in single processors namely drowsy cache and gated- VDD will be examined for NOC’s (Network on-Chip) and Chip Multiprocessors (CMP) systems; the reason being that both techniques are widely used in microprocessors and performance trade off considering power consumption and speed improvement is always a primary concern for high performance integrated circuits. The rest of the paper is organized as follows. Section II gives a brief overview of different low-power designs proposed over the years. Section III explains the Network-on-Chip (NOC) concept and one of its basic mesh structures. The leakage power of buffers in NOC’s is studied and the impacts of drowsy and gated-VDD are examined. A similar approach is investigated on multi-core processors, and the affects of incorporating circuit level mechanisms is explored in section IV. Section V provides the direction of future research. Finally section VI concludes the paper. II. LEAKAGE REDUCTION TECHNIQUES IN CACHE MEMORY AND MULTI-CORE PROCESSOR ARCHITECTURE Depending on different applications of CMOS devices, various techniques for leakage reduction have been proposed in the literature. In this section, some effective and popular methods for leakage power reduction in cache memories and multi-core processors have been briefly described. A. Multi-Threshold CMOS SRAM Although lower threshold voltage boosts up the transistor speed, it increases the sub-threshold current which is the major component of total leakages. Considering this factor, a multi-threshold technique is proposed in CMOS SRAM where low-V th transistors are used when very high circuit speed is required [2]. An SRAM consists of six transistors and produces high leakage power; therefore, it is a very effective technique to control leakage power in SRAM modules. As shown in Figure 1, all active circuit components are connected to power supplies through virtual power supply lines. Figure 1: Circuit configuration of Multi-Threshold CMOS SRAM The high-V th transistors act as sleep/control transistors that link the real and virtual power lines. The MTCMOS technique cuts off the power supply to the memory cells destroying their states. The use of high-V th transistors significantly reduces the leakage power. ϒ Currently with Hewlett-Packard, Inc., USA (sandhya.jeevan@hp.com). This work is condensed from her research conducted at UIC. 2008 International Conference on Microelectronics 1-4244-2370-5/08/$20.00 ©2008 IEEE 163