Chapter 1 Configurable Models and Design Space Exploration for Low-Latency Approximate Adders Muhammad Abdullah Hanif, Rehan Hafiz, and Muhammad Shafique 1.1 Introduction to Low-Latency Adders Addition is one of the most commonly used operations in almost all the data processing-related applications. High-performance adders have become signifi- cantly common for applications that require low latency and/or high throughput. One of the common types of such adders, which has proven to be highly effective for improving the latency of the systems, is fast/parallel-prefix adders. While these adders can provide effective performance benefits, they do introduce significant power and area overhead due to the requirement of parallel carry generation logic. Coincidentally, most of the applications which involve intensive data processing are somewhat resilient to errors and therefore can leverage the concepts of approximate computing to achieve significant performance improvements [1–4]. Several high-performance approximate adders have been proposed, for example, ETA-II [5], ETA-IIM [5], ACA [6, 7], GDA [8], etc. that improve the performance of adder blocks beyond that of the conventional accurate designs. Each approximate low-latency adder has its own unique error, performance, area, and power character- istics and, therefore, are suitable for different scenarios. Almost all such adders can be categorized under the umbrella of block-based adders, as they employ smaller sub-adder units/blocks which operate in parallel to compute the resultant bits of the output. A few example approximate low-latency adders are shown in Fig. 1.1. M. A. Hanif () · M. Shafique Vienna University of Technology (TU Wien), Vienna, Austria e-mail: muhammad.hanif@tuwien.ac.at; muhammad.shafique@tuwien.ac.at R. Hafiz Information Technology University (ITU), Lahore, Pakistan e-mail: rehan.hafiz@itu.edu.pk © Springer Nature Switzerland AG 2019 S. Reda, M. Shafique (eds.), Approximate Circuits, https://doi.org/10.1007/978-3-319-99322-5_1 3