Dynamic Branch Prediction Study Combining Perceptrons and Bit-Counter Predictors Lisa M. Alano, Brad S. Boven, Andy R. Terrel August 19, 2007 Abstract Current processors use two bit counters for branch prediction; however, recent literature has established that the perceptron learning algorithm, a supervised learning technique, render more accurate predictions. We attempt to integrate both approaches to improve prediction accuracy through four hybrid predictors based on the 2bc-gskew predictor. In all conﬁgurations, a single perceptron predictor is still more accurate leading to an analysis of how the technologies behind perceptrons and bit counters interact. 1 Introduction Modern processors rely on sophisticated mechanisms to exploit instruction level parallelism (ILP). For example, processors resolve control hazards by attempting to predict whether a branch will be taken or not. This technique, which is called branch prediction, which decreases potential stalls caused by control dependences. But as hardware designers pave the way for even more ILP through pipelining and other dynamic schemes, the impact of control dependencies on the eﬀectiveness of a processor grows. Furthermore, as pipeline depths increase, the penalty for a missed prediction becomes more severe, heightening the demand for accurate predictions. However, as clock cycle time decreases and processor speeds 1