Performance Analysis of System-on-Chip Architectures for Ultrasonic Data Compression Boyang Wang * , Pramod Govindan ** and Jafar Saniie * * Embedded Computing and Signal Processing Laboratory Department of Electrical and Computer Engineering Illinois Institute of Technology, Chicago, Illinois ** School of Engineering University of North Florida Jacksonville, Florida Abstract—Ultrasonic NDE and imaging applications utilize a large amount of information. Most of these applications demand real-time data processing with low power consumption. Compression of the collected ultrasonic data helps to reduce the storage, as well as rapid data transmission to remote locations for expert analysis. The objective of this study is to develop embedded system-on-chip architectures for ultrasonic data compression, and analyze the performance of different design methods according to the application requirements. The system is implemented using Xilinx Zynq System-on-Chip (SoC), which combines both ARM processor and field-programmable gate array (FPGA) on the same chip. The major parameters analyzed in this study are signal fidelity, hardware resource utilization and computational processing speed. The hardware and software co-design implementation is about five times faster compared to software only implementation using Zynq SoC. Keywords - Ultrasonics; Data Compression; FPGA; Zynq SoC I. INTRODUCTION The ultrasonic testing platform demands high sampling rates and computational speed in order to realize real-time processing. This paper explores the implementation of ultrasonic signal acquisition and processing on Xilinx Zynq System-on-Chip (SoC) platform [1]. In our previous work [2], the system architecture of a reconfigurable ultrasonic testing system is presented, where the hardware setup of this system is introduced. Figure 1 shows the block diagram of the ultrasonic testing system. The system is capable of generating and capturing high frequency ultrasonic echoes. With a high speed ADC interfaced to the system through FPGA, the system will sample the high frequency ultrasonic echoes at 250MSPS, where each sample consists of 16 bits. The sampled data will be buffered and processed on the Zynq SoC. In this study, a low cost Zynq based development board called Zedboard is used as the main controller and processor of the system. Section II discusses the efficiency of various ultrasonic data compression algorithms. In this study, ultrasonic data compression is implemented by using three processing methods: discrete wavelet transform (DWT), Frequency domain windowing, and signal decimation in time domain. Section III presents the implementation of the compression algorithms on Xilinx Zynq SoC which consists of a powerful dual-core ARM embedded processor and programmable FPGA to support hardware-software co-design. Time-consuming computational operations such as FFT and Inverse FFT (IFFT) are realized in FPGA by using Xilinx IP cores available within Zynq to achieve accelerated data processing with high accuracy. Moreover, the direct memory access (DMA) module available within Zynq is utilized for high speed memory transfer between the embedded ARM processor and the external DDR RAM, which helps to improve the overall system performance. FMC CONNECTOR ZEDBOARD T/R switch TX810 LNA/VCA VCA8500 AD9467 FMC CARD PC Power Supply Amplified Target Signal High Speed Pulser MD1822DB2 Steel Block To Ultrasonic Transducer X Y Z Water Tank SPI GPIO T-Shape Connector Figure 1. Ultrasonic Testing System Block Diagram [2] II. INTRODUCTION TO COMPRESSION ALGORITHMS This section details three different compression algorithms which have been explored in this study. 978-1-4673-9897-8/16/$31.00 ©2016 IEEE 2016 IEEE International Ultrasonics Symposium Proceedings Authorized licensed use limited to: Illinois Institute of Technology. Downloaded on October 02,2020 at 15:10:06 UTC from IEEE Xplore. Restrictions apply.