Research Journal of Applied Sciences Engineering and Technology 4(7): 819-824, 2012 ISSN: 2040-7467 © Maxwell Scientific Organization, 2012 Submitted: November 15, 2011 Accepted: December 09, 2011 Published: April 01, 2012 Corresponding Author: M.D. Mamun, Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600, UKM, Bangi, Selangor, Malaysia, Tel.: +603-89216316; Fax: +603-89216146 819 Single Core Hardware Modeling of Built-in-Self-Test for System on Chip Design M.D. Mamun, M.S. Amin and J. Jalil Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600, UKM, Bangi, Selangor, Malaysia Abstract: This study describes a hardware modeling environment of built-in-self-test (BIST) for System on Chip (SOC) testing to ease the description, verification, simulation and hardware realization on Altera FLEX10K FPGA device. The very high speed hardware description language (VHDL) model defines a main block, which describe the BIST for SOC through a behavioral and structural description. The three modules test vector generator, circuit under test and response analyzer is connected using its structural description. 8-bit pseudorandom test vector generator is a linear feedback shift register circuit consists of D latches and XOR gates produces 255 different patterns of test vectors for CUT which consists of a 3 to 8 line decoder and a 4 bit adder circuit. In response analyzer, the multiple-input pattern compressor circuit is used to produce signature and a comparator circuit is used for signature analysis. The design is modularized and each module is modeled individually using hardware description language VHDL. This is followed by the timing analysis and circuit synthesis for the validation, functionality and performance of the designated circuit, which supports the practicality, advantages and effectiveness of the proposed hardware realization for the applications with a maximum clock frequency of 31.4 MHz. Key words: Built-in-self-test, circuit under test, design for testability, latches, system on chip, VHDL INTRODUCTION One of the most widely researched self-testing techniques is built-in-self-test (BIST), which uses embedded hardware test generators and test response analyzers to generate and apply test patterns on-chip at the speed of the circuit, thereby eliminating the need for an external tester (Yuejian et al., 2011; Tseng et al., 2010). BIST techniques can be classified into two categories, namely on-line BIST and off-line BIST (Lusco et al., 2011; Abramovici, 1990). Embedded BIST functions match the chip's capabilities, which can make them very effective testing mechanisms. Also, BIST stays with the chip throughout its life. Moreover, the addition of BIST features to electronics hardware frequently doesn't significantly increase a product's size, cost, and production time, as was the case in the past. Adopting BIST and DFT (Design for Testability) is accompanied by size overhead and delay. But many companies are adopting them to reduce the testing cost. For example, Intel is adopting the BIST (Built-In Self Test) technique from 80386, boundary scan in the Pentium processors (Needham and Gollakota, 1996). Sun microsystems were adopting the BIST technique and boundary scan in the SuperSPARC and SuperSPARCII (Rajiv and Yarlagadda, 1993; Hong and Avra, 1995). FPGA offers a potential alternative to speed up the hardware realization. From the perspective of computer- aided design, FPGA comes with the merits of lower cost, higher density, and shorter design cycle. It comprises a wide variety of building blocks. Each block consists of programmable look-up table and storage registers, where interconnections among these blocks are programmed through the hardware description language (Reaz et al., 2007). This programmability and simplicity of FPGA made it favorable for prototyping digital system. FPGA allows the users to easily and inexpensively realize their own logic networks in hardware. FPGA also allows modifying the algorithm easily and the design time frame for the hardware becomes shorter by using FPGA (Akter et al., 2008). Several methodologies for testing of microprocessors have been presented in recent years and almost these methods have area and performance overhead (Shen and Su, 1988; Talkhan et al., 1989; Hetherington et al., 1995). Since the need for self testing is most acute for high performance processors, this research propose a model of built-in-self-test for system on chip using VHDL. The use of VHDL for modeling is especially appealing since it provides a formal description of the system and allows the use of specific description styles to cover the different abstraction levels (architectural, register transfer and logic