928 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 12, DECEMBER 2003 A New Low Voltage Precision CMOS Current Reference With No External Components Rasoul Dehghani and S. M. Atarodi Abstract—A novel current reference with low temperature and supply sensitivity and without any external component has been developed in a 0.25 mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit sim- ilar to a beta multiplier. An NMOS transistor in triode region has been used in place of a resistor in conventional beta multiplier to achieve a current which has a negative temperature coefficient and only oxide thickness dependent. The BGR voltage has a positive temperature coefficient to cancel the negative temperature coeffi- cient of the beta multiplier. The simulation results using Bsim3v3 model show max-to-min fluctuation of less than 1% over a temper- ature range of to and a supply voltage range of 1.4 V to 3 V with tolerance for all of the used on-chip resis- tors. The maximum current variation is slightly less than the oxide thickness variation in the process corners. I. INTRODUCTION C URRENT reference as an essential block in analog IC’s is needed in many analog signal processing applications such as operational amplifier and data converter bias circuits. Reference currents are often implemented by applying a bandgap voltage reference across a resistor. The main problem corresponding to this method concerns the used resistor. On-chip resistors are typically highly process-dependent, while off-chip resistors are not suitable due to cost and area considerations. Replacing resistor with its switched capacitor equivalent requires a separate frequency clock source and on-chip capacitors that leads to complexity and large area [1], [2]. Added digital noise to the circuit is another disadvantage of the switched capacitor method. This work circumvents the need for an accurate on-chip re- sistor without using any external component. In Section II, gen- eral architecture of the proposed current reference is reviewed and the corresponding relations are derived. Section III is de- voted to the description of the current reference components in- cluding BGR circuit, quasi CMOS beta multiplier, operational amplifiers, and startup circuit. The simulation results are pre- sented in Section IV and conclusion is made in Section V. Manuscript received February 18, 2003. The authors would like to express their thanks to EMAD SEMICON CO. for financial supports. This paper was recommended by Associate Editor B. Razavi. The authors are with the Department of Electrical Engineering, Sharif Uni- versity of Technology, Tehran, Iran 1 (e-mail: dehghani@mehr.sharif.edu). Digital Object Identifier 10.1109/TCSII.2003.820239 1 Note: New regulations imposed by the U.S. Government placed severe re- strictions on the review process for this paper and prevented the editorial staff of the journal from making any corrections to the paper. Please see the Editorial in this issue for more details. Fig. 1. Architecture of the proposed current reference. II. CURRENT REFERENCE ARCHITECTURE The proposed architecture is composed of two main parts as shown in Fig. 1. The first part is a BGR circuit with a positive temperature coefficient output voltage Vr and the second part is a quasi CMOS beta multiplier in which the resistor in con- ventional one has been replaced by an NMOS transistor (M1). The drain-source voltage of M1 is controlled by Vr in a nega- tive feedback loop established by the operational amplifier OP. The voltage Vr is less than M1 drain-source saturation voltage ( ), therefore, M1 operates in triode region. For M1 with adequately long channel length, the drain current can be written as follows (1) Where: . is the inversion layer mo- bility, is the gate oxide capacitance per unit area, is the threshold voltage, and are the width and length of , respectively. On the other hand, diode connected is in satu- ration region and its current is (2) Noting that , and , from (1) and (2) the following relation is derived (3) where and is the output current. For we have (4) is a process independent voltage and has a low depen- dency on process variations, thus the oxide thickness is the only 1057-7130/03$17.00 © 2003 IEEE