Copyright © 2018 Authors. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. International Journal of Engineering & Technology, 7 (2.8) (2018) 413-418 International Journal of Engineering & Technology Website: www.sciencepubco.com/index.php/IJET Research Paper Design and comparative analysis of inexact speculative adder and multiplier K. Hari Kishore, B. K. V. Prasad, Y. Manoj Sai Teja*, D. Akhila, K. Nikhil Sai, P. Sravan Kumar VLSI Research Group, Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India 522502 *Corresponding Author Email: manojsaiteja@gmail.com Abstract A Carry look ahead adder is a sort of the summer used in the logic design of the digital systems. The CLA boost up the speed by decreasing the measure of duration needed to calculate the carry bits. The CLA based outline of the inexact speculative adder is pipelined architecture to incorporate couple of logic paths along its basic way and in this manner, improving the recurrence of operation. This paper presents the comparative analysis of the pipelined inexact speculative adder and the general carry look ahead adder and showed that the delay is reduced to 48.27% when compared to carry look ahead adder and also we have designed the pipelined multiplier using the Inexact speculative adders and observed that the delay is reduced to 48.32% when compared to the normal multiplier. This entail Xilinx ISE Design Suite 14.5 Tool. Keywords: Inexact Speculative Adder, Multiplier, Carry Look Ahead Adder, Pipelining, Delay. 1. Introduction The inexact speculative adder is designed in such a way that the carry propagation chain is splitted into multiple paths which are concurrently executed. Each path again contains a error compensation block, sub-adder block and a carry speculator block. The partial signal is generated by the speculator block and to give the local sum the sub adder block uses carry in. Faulty sums are corrected by the compensation block which corrects either local sum or reduces the magnitude in the error. The carry for speculation block is generated by using the bits in carry look ahead sourced either by dynamic or static input. Errors are distributed evenly by the latter in ETBA. Speculation faults are detected by the COMP block by comparing carry out and generated carry from the speculation block. The COMP block is implemented between ADD blocks. The addition is implemented by following five steps mainly. First for each sub-adder block , a carry-in is speculated from short carry propagation chain and next based on that carry in local sum is calculated by the sub adder. Faulty speculation is detected by comparing the carry in and the carry out of the sub adder. Correction of local sum is done when there is wrong speculation. Error magnitude is minimized by the balance of preceding sum bits if the correction is not possible. The inconsistency between expected carry and speculated carry is detected by the COMP block by using the XOR gate because of which error flag is created that triggers activation either error reduction or correction compensation techniques. The three main advantages of this technique is that optimization of block size, speculation and correction trade-off and error minimization and failed correction [1]. In the speculative addition with the variable latency CSPA block has carry and adder circuits. Carry predictor helps in prediction of carry out bit. And adder has three internal components namely multiplexer which consists of multi bit, the sum generator and also an internal carry generator. Carry out bit of the adder block is predicted by the carry predictor. Internal signals to be used in the sum generator are produced by the internal carry signals. Multiplexer takes the input from the carry predictor and selects on of the carry signals. Sum generator calculates the partial sum bits of adder block. The proposed method works as follows, internal carry generators and predictors work simultaneously when input patterns arrive. The carry out bit of the predictor is given to next block adder and it is the selector for multiplexer and next internal carry signal is determined and is sent to the sum generator. Error recovery and detection circuit is also used. Error signal is 0 when there is no error and valid signal becomes 1 when an error occurs error and valid signal becomes vice versa during error input registers becomes disable and no input is taken [2]. The carry speculative adder with modification of carry generators that uses only less number of gates. In order to get data continuously into circuit the data latching circuit is used. To get results accurately the error recovery and detection circuit is included. The CSPA is implemented in a way that in the modified adder block sum and carry generators are separated by an logic which results in increase of area and consumption of power. To minimize the area two carry generators are for carry in=1 and carry in=0 used instead of one. AND gate is replaced in the place of 1bit carry generator for carry in=1 and carry in=0 it is replaced with OR gate. Two types of modified carry generators are used in place of two carry generators which has one gate delay with very less area. These generators produce carry without using Cin bit. In the design of variable latency CSPA the circuits such as error recovery, error detection, data latching are used [3]. When the input is received the output sum is given by the circuit (VLCSPA). Error block signals and error signals is given by the error detection circuit. Multiplexer which is multibit takes the input from the recovery circuit and cspa when it is 1 signal recovery is from recovery circuit and when it is 0 result is selected from CSPA. Input registers become disabled when an error occurs and no input is taken and XOR gate is used in place of not gate and ex-or operation is used between error signal and its compliment.