Design, Development and Validation of Fault-Tolerant Processor and Integrated Development Environment for Space and Defence Applications: Indigenous Initiative P. Balasubramanian, B. Kusuma Kumari, S. Kalyan Kumar, Anil N. Terkar, Chnab Sankar, Sudhanshu Kumar, Vikram Singh Parihar,J. V. R. Sagar and C. Ramesh Reddy Abstract Space and defence electronics system demands higher reliability for its operation in harsh (Maurer et al. in John Hopkins APL Tech Dig 28, 2008 [1]) and tough application environments. Development of processor (Azambuja et al. in IEEE Trans Nucl Sci 59, 2012 [2]) based electronics systems has advantages over sequencer logics, viz. high operating frequency, handle complex algorithm for autonomous operations, supports multiinput and multioutput systems, low form fac- tor, ultra-low-power consumption and increased reliability. The operation of pro- cessor under various environmental conditions and its uninterrupted operations pave way to achieve successful missions. Most of the on-board computers for the space and defence systems are subjected to harsh environments due to cosmic radiations(aerial), high temperature, vibrations, sand and dust. Modular redundancy concepts aid to improve reliability however at the cost of increased form factor and enhanced power requirements. Researchers across the globe evolved with various methods and tech- niques to increase the ruggedness of the electronics systems. Traditional design hard- ening techniques viz. modular redundancies, parity algorithms, cyclic redundancy checks, single error correction and double error detection are in use to develop the fault-tolerant on-board computers. Since most of the fault-tolerant processors devel- oped using in-house design, process hardening techniques for specific purpose, the availability of the same for the strategic programs and critical applications is limited P. Balasubramanian DRDO Research and Innovation Centre (RIC), IIT Madras Research Park, Chennai 600113, India e-mail: pbalasubramanian@ric.drdo.in B. Kusuma Kumari · S. Kalyan Kumar · A. N. Terkar (B ) · C. Sankar · S. Kumar · V. S. Parihar · J. V. R. Sagar ANURAG, Hyderabad, India e-mail: a_terkar@anurag.drdo.in B. Kusuma Kumari e-mail: kusuma@anurag.drdo.in C. Ramesh Reddy RCI, Hyderabad, India © Springer Nature Singapore Pte Ltd. 2020 PSR. S. Sastry et al. (eds.), Advances in Small Satellite Technologies, Lecture Notes in Mechanical Engineering, https://doi.org/10.1007/978-981-15-1724-2_40 413