SPAA’21 Panel Paper: Architecture-Friendly Algorithms versus Algorithm-Friendly Architectures Guy Blelloch Computer Science Carnegie Mellon University Pittsburgh, PA guyb@cs.cmu.edu William Dally NVIDIA Santa Clara, CA dally@stanford.edu Margaret Martonosi Computer Science Princeton University Princeton, NJ mrm@princeton.edu ABSTRACT The current paper provides preliminary statements of the panelists ahead of a panel discussion at the ACM SPAA 2021 conference on the topic: algorithm-friendly architecture versus architecture-friendly algorithms. CCS CONCEPTS  Architectures  Design and analysis of algorithms  Models of computation KEYWORDS Parallel algorithms; parallel architectures ACM Reference format: Guy Blelloch, William Dally, Margaret Martonosi, Uzi Vishkin and Katherine Yelick. 2021. SPAA’21 Panel Paper: Architecture-friendly algorithms versus algorithm-friendly architectures. In Proceedings of the 33rd ACM Symposium on Parallelism in Algorithms and Architectures (SPAA ’21), July 6–8, 2021, Virtual Event, USA. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/3409964.3461780 1 Introduction, by Uzi Vishkin The panelists are: - Guy Blelloch, Carnegie Mellon University - Bill Dally, NVIDIA - Margaret Martonosi, Princeton University - Uzi Vishkin, University of Maryland - Kathy Yelick, University of California, Berkeley As Chair of the ACM SPAA Steering Committee and organizer of this panel discussion, I would like to welcome our diverse group of distinguished panelists. We are fortunate to have you. We were looking for a panel discussion of a central topic to SPAA that will benefit from the diversity of our distinguished panelists. We felt that the authentic diversity that each of the panelist brings is best reflected in preliminary statements, expressed prior to start sharing our thoughts, and, therefore, merits the separate archival space that follows. 2 Preliminary statement, by Guy Blelloch The Random Access Machine (RAM) model has served the computing community amazingly well as a bridge from algorithms, through programming languages to machines. This in large part can be attributed to the superhuman achievements by computer architects in maintaining the RAM abstraction as technology has advanced. These efforts include a variety of approaches for maintaining the appearance of random access memory, including sophisticated caching and paging mechanisms, as well as many developments to extract parallelism from sequences of RAM instructions, including pipelining, register renaming, branch prediction, prefetching, out-of-order execution, etc. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from Permissions@acm.org. SPAA ’21, July 6–8, 2021, Virtual Event, USA. © 2021 Copyright is held by the owner/author(s). Publication rights licensed to ACM. ACM ISBN 978-1-4503-8070-6/21/07...$15.00. https://doi.org/10.1145/3409964.3461780 Uzi Vishkin University of Maryland Institute for Advanced Computer Studies (UMIACS) College Park, MD Contact author: vishkin@umd.edu Katherine Yelick Electrical Engineering and Computer Sciences University of California Berkeley, CA yelick@berkeley.edu