399 Measuring the Tolerance of Self-adaptive Clocks to Supply Voltage Noise Jordi Pérez-Puigdemont, Francesc Moll Dpt. of Electronic Engineering, Universitat Politécnica de Catalunya - C/ Jordi Girona 1-3 08034 Barcelona jordi.perez-puigdemont@upc.edu | francesc.moll@upc.edu Jordi Cortadella Dpt. of Languages and Informatics Systems, Universitat Politécnica de Catalunya - C/ Jordi Girona 1-3 08034 Barcelona jordi.cortadella@upc.edu Abstract—Simultaneous switching noise has become an impor- tant issue due to its signal integrity and timing implications. Therefore a lot of time and resources are spent during the PDN design to minimize the supply voltage variation. This paper presents the self-adaptive clock as an alternative to tolerate the critical path delay variation due to supply noise thanks to its self-adaptable nature. A self-adaptive clock generation circuit is proposed in this paper and its benefits, in terms of clock period reduction, are assessed under a realistic supply noise obtained through simulation for different switching activities. I. I NTRODUCTION The synchronous system paradigm continues to be the basis of today’s sequential system design. In this paradigm the clock period is fixed and determined by the critical path delay plus setup time of registers and a timing margin to accommodate for worst case conditions. In current and new technologies, process variations [1], [2] introduce a large uncertainty in the gate delay, which could be up to 30%, [3], [4] and therefore a larger timing margin, ΔT PV , must be added to the clock period. In some circuits this added margin accounts for a loss of performance. In addition to process variations, voltage variations introduce a second source of added timing margin, ΔT VV , which, as is shown in fig. 2, could be up to 50% of the nominal delay. In order to minimize the effects of power supply noise a large design effort is dedicated to the power supply distribution [5], [6], including the use of on-chip decoupling capacitors [7], [8]. The use of decoupling capacitors present a drawback in terms of area overhead and increase of leakage. The objective of this paper is to evaluate the use of a self adaptive clock as a way to tolerate a larger power supply noise originating from simpler power distribution network or a smaller quantity of decoupling capacitance. A self-adaptive clock is a clock that its period suffers a variation correlated to the delay variations of the critical path, caused either by process or by supply voltage variations. If the correlation is high it means that even for important voltage fluctuations the circuit will still behave correctly because the clock period will be larger when the critical path is slower and viceversa. This approach aims to reduce as much as possible the time guards ΔT VV and ΔT PV introduced due to the delay uncertainty caused by voltage or process variations                Fig. 1. Scheme of GALS circuit. The different synchronous clock domains are communicated with the following domains through asynchronous FIFO queues. This queues isolated the different clock domains in term of timing constrains. Therefore each domain can be studied separately. respectively. In the current article we will focus only on the reduction of ΔT VV due to supply voltage variation. The studied approach is focused on globally-asynchronous locally- synchronous (GALS) architectures [9] depicted in Fig. 1, even though the results can be easily extended to asynchronous circuits with bundled data and matched delays [10]. In the GALS architecture the whole circuit is divided in different clock islands, operating synchronously at internal level, that communicate in an asynchronous way. In this paper we propose a self-adaptive clock to act as the locals clocks in the GALS architecture. The proposed mechanism is self-compensating in the sense that no external control is necessary and the clock frequency self-adjusts to the existing variations in the critical path. Moreover, the self-adaptive clock scheme allows a relaxation in the Power Distribution Network (PDN) rules resulting in shorter design times, less on-chip decoupling capacitors, or lower operating voltages and consequently a decrease in power. This work is structured in four sections. In the first we develop the concept of self-adaptive clocks. After that we focus on how the supply voltage variation is modelled. In the third section we assert the benefits of the self-adaptive clock scheme through two ways: analysing the correlation between the supply voltage waveforms of the self-adaptive clock and critical path and the delay variation produced by the supply noise. Finally we summarize our results in the conclusions.