Innovative Systems Design and Engineering www.iiste.org ISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol.5, No.4, 2014 84 Design of Low Offset and High Speed CMOS Comparator for Analog to Digital Converter Nidhi Tarun, Shruti Suman, P. K. Ghosh ECE Department Faculty of Engineering and Technology Mody University of Science and Technology Lakshmangarh, Sikar, Rajasthan, India shrutisuman23@gmail.com Abstract In today’s world everything is digitized but nature is analog, so it is necessary to have such a device which converts analog signal into digital and for this analog to digital converter is required. Now a day’s ADC’s require lesser power, better slew rate, high speed and less offset. Performance limiting component for ADC’s are amplifiers and comparators in which comparator is the most important.This paper presents the design of low offset low power dissipation and high speed comparator. The proposed comparator consists of a preamplifier stage, decision stage and self biased output buffer stage. The proposed design uses a low power current mirror circuitry for providing a highly biased current. The circuit is designed using 90nm CMOS process for a supply voltage of 1V and reference voltage of 0.5V and power consumption is approximately 300μW. Keywords: CMOS Comparator, Current Mirror, Pre Amplifier, Output Buffer \ 1. Introduction The recent advancements in technology prove that we are working in the digital world, but we know that all the signals are analog in nature. So, it is necessary to have a device, which converts all the analog signals into digital. For this purpose, we use an Analog-to-Digital Converter (ADC) [Paul R Gray, Paul J Hurst, Stephen H Lewis and Robert G Meyer (1984), Hao Gao, Baltus,p ,Qiao- meng, (2010)]. The basic component in ADC device is a comparator. Figure1 shows comparator symbol. Many comparators have been proposed earlier. Among the circuits proposed, some are concerned with speed, some emphasizing on low power and high resolution, and some on offset cancellation [Jia-chen, Kurachi,S, Shimin Shen (2005)]. Bang-Sup Song proposed a comparator circuit with only preamplifier and decision stage, but did not provide any experimental results to analyze the circuit performance [Bang-Sup Song, Seung-Hoon Lee and Michael F. Tempsett (1990)]. Amalan Nag proposed a comparator with 200 MHz speed and with offset cancellation [Amalan Nag, K. L. Baishnab F. A. Talukdar, (2010)]. Allstot also thought of and simulated a novel comparator circuit which has cascading stages and ended up with a minimum power supply requirement of 3.5 V. The resolution may be higher but achieved at the expense of bulky cascading stages [David J. Allstot (1982)]. The comparator basically can be decomposed into three stages shown in Figure 2. The stages are input stage, decision stage, output stage. Designing a comparator can begin with considering input common-mode range, power dissipation, propagation delay, and comparator gain. The rest of the paper is organized in nine different sections: Circuit description of comparator and proposed Current mirror in section 2 and 3. Design of pre-amplifier using proposed current mirror and comparator circuit is described in section 4 and 5. Simulation results are discussed in section 6 and finally, section 7 provides conclusion. 2. Circuit Description This design consists of three stages; the first stage is the preamplifier, followed by a positive feedback or decision stage, and an output buffer. The preamplifier stage amplifies the input signal to improve the comparator sensitivity. Output of pre-amplifier goes into decision block where comparator makes decision that which of the input signals is large. The decision stage is non-linear cross-coupled circuit which switches from one state to another. The output stage buffer the decision stage and convert the signal level to digital signal level [Wen-Rong Yang, Jia-dong Wang (2007)]. 2.1. Pre-Amplifier A preamplifier is an amplifier that prepares a small electrical signal for further amplification or processing. A preamplifier is often placed close to the sensor to reduce the effects of noise and interference. It is used to boost the signal strength to drive the cable to the main instrument without significantly degrading the signal-to-noise ratio (SNR).When the gain of the preamplifier is high, the SNR of the final signal is determined by the SNR of the input signal and the noise of the pre-amplifier. The main criteria for designing a pre-amplifier are its gain