A Structured System Methodology for FPGA Based System-on-a-Chip Design Pete Sedcole, Peter Y. K. Cheung, George Constantinides & Wayne Luk Imperial College, Exhibition Road London SW7 2BT, UK The ever increasing quantities of logic resources com- bined with heterogeneous integrated performance enhanc- ing primitives in high-end FPGAs creates a design complex- ity challenge that requires new methodologies to address. We present a structured system based design methodology which aims to increase productivity and exploit reconfigura- bility in large scale FPGAs. The methodology is exemplified by Sonic-on-a-Chip, a video image processing system. 1. Introduction The continuing compound growth in transistor density due to advances in process technology is not being matched by a corresponding growth of integrated circuit designer productivity. The increase in the cost of application spe- cific IC design is a primary threat to the semiconductor roadmap [4], a problem compounded by increasing mask set costs, long design, fabrication and test cycles, and the inflexibility of the end product. Field Programmable Gate Arrays are regarded as a panacea for these problems, since their regular structure and scalability facilitates silicon de- sign and test. However, escalating FPGA heterogeneity due to the integration of performance enhancing primi- tives (such as memories and microprocessors) coupled with increasing transistor density results in a design complex- ity challenge, necessitating the development of new design methodologies to increase productivity. We present a structured system design methodology based on a paradigm of architecture reuse; instead of de- signing a system in an FPGA from the bottom-up by con- necting together blocks of predesigned IP in an ad hoc man- ner, the system is constructed from the top-down by defin- ing the logical and physical structure (i.e. the architec- ture) first. Key aspects of the methodology are the use of modularity, high levels of abstraction and orthogonalisa- tion of concerns, such as the separation of communication and computation, thus avoiding system-level timing closure issues. The methodology enables reconfigurability to be ex- ploited for customisation and in-field partial upgrades. Since the methodology is based on architectural reuse, the choice of architecture is critical; we exemplify the methodology with a single architectural instance Sonic-on- a-Chip [3], a video processing system based on Sonic [1]. The architecture comprises several layers. Logical and physical layers describe the system topology and infrastruc- ture, and combined form a platform for application develop- ment. Applications built on the platform include hardware modules, operating system layers and algorithm encoding. 2. Sonic-on-a-Chip Logical layer: The general logical layer for Sonic-on-a- Chip is shown in Figure 1. The operation of this system and its optimisations for video processing has been described previously [3]. However, it should be noted that (a) system- level design is facilitated by inherent modularity, (b) the number and complexity of each modular processing ele- ment (PE) may vary, (c) within each PE, a router (fixed in design but programmable) is used to manage communica- tion, separating this from the computation being performed in the fully customisable engine. Furthermore, data are passed into and out of the engine via stream buffers which, being composed of RAM primitives may be formed into a number of different configurations (a two-input two-output option is depicted in the diagram). Physical layer: The physical layer of the architecture defines the implementation of the logical system structure on the FPGA, including the positioning of the modules and the intermodular routing. It is possible to integrate the in- frastructure and modules together at design time (during synthesis or as netlists). In our methodology the integra- tion is at run-time, which we term late integration. This increases the advantages of modularity and enables systems to be rapidly constructed (with no further hardware design) from pre-implemented modules. Importantly, to achieve late integration of a variable number of modules of different sizes, system-level intermodular routing is fixed and regu- lar, which leads to deterministic timing. In this respect our implementation is similar to DISC [5], although on a larger scale. Application implementation: Applications for Sonic- on-a-Chip must be expressible in dataflow graph format, Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’04) 0-7695-2230-0/04 $ 20.00 IEEE Authorized licensed use limited to: IEEE Xplore. Downloaded on February 17, 2009 at 11:29 from IEEE Xplore. Restrictions apply.