506 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 15, NO. 5, MAY 1996 Hierarchical Tolerance Analysis Using Statistical Behavioral Models Timo Koslunen and P. Y. K. Cheung zyxwv Abstract- zyxwvutsrqpon A methodology is presented for deriving statistical models of analog and digital circuit cells at the behavioral level. These models can be combined in a single simulation environment for efficient yield estimation of large circuits. The motivation is the growing importance of mixed analog/digital ASIC’s and the impracticality of traditional approaches to tolerance analysis based on computationally intensive device-level simulation. An efficient method of mapping from device-level space to behavioral space which requires no a priori assumption about the analyt- ical mapping is presented. The method is demonstrated using an operational amplifier example. By combining the mapping with statistical methods, tolerance information is included in the behavioral model. A statistical model giving the mean, standard deviation, and correlation of behavioral parameters is obtained. Hence the tolerance analysis problem can be defined at the be- havioral level of simulation and the statistical behavioral models combined to estimate the variation of system level performance. This hierarchical methodology is demonstrated using a two-stage flash analog-to-digitalconverter circuit. Compared to device-level simulation, a fifteen-foldgain in efficiency,and accuracy to within 2% were achieved in the yield estimate using a static performance specification. I. INTRODUCTION OLERANCE analysis is concerned with estimating the T variation in the performance of an electronic integrated circuit. This variation is due to disturbances in the manufactur- ing process which affect all fabricated samples differently. zyxwvu As a result, it is possible that for some samples, the circuit does not perform satisfactorily, and the yield is less than 100%. The disturbances causing yield loss are either spot defects which may lead to catastrophic failure, or variations in the process parameters which may lead to parametric failure. In the latter type of failure, the circuit typically functions as desired, but circuit specifications such as gain or bandwidth are not met. Only parametric failure is considered in the yield measure used in this paper, as it is a function not only of the disturbances but also of the designable circuit parameters (transistor lengths and widths) and the circuit specification. A statistical model of the electrical device parameters, such as threshold voltage and doping density, is used to capture the manufacturing disturbances. These parameter disturbances have a global component which is constant across a given die Manuscript received April 8, 1994; revised May 5, 1995 and January 18, 1996. This paper was supported by the SERC under the CHIPAIDE project. This paper was recommended by Associate Editor R. A. Saleh. T. Koskinen is with Siemens ON TN ETD 7, Public Communications Networks, Design Centre ASIC, 81359 Munich, Germany. P. Y. K. Cheung is with the Information Engineering Section, Department of Electrical and Electronic Engineering, Imperial College, University of London, SW7 2BT, England. Publisher Item Identifier S 0278-0070(96)04639-8. and a local component which varies from device to device. While the local variation tends to be far smaller than the global variation, both need to be considered in designs where device mismatch is critical to circuit performance. Statistical methods have been developed for estimating the circuit performance spread and hence the parametric yield prior to fabrication zy [ 11-[3]. However, traditional methods are based on device- level simulation of a flat netlist and are only tractable for small circuits. In order to reduce the computational cost, hierarchical methods involving high-level circuit modeling techniques have been proposed. An early approach to using higher-level circuit models in tolerance analysis involved an application of the control variate method [4]-[6], the principal aim of which is to reduce the computational cost of the Monte Carlo analysis. The starting point is a circuit model, typically a SPICE model zy [7], giving accurate performance prediction, and a second system, the much simpler control variate system, or shadow model, which represents the same circuit behavior, but is computationally much less expensive to analyze. The main ‘many-sample’ Monte Carlo experiment is conducted using the simpler shadow model which allows the yield to be estimated efficiently. A second Monte Carlo experiment that is conducted on both models using identical random samples allows a correction to be made to the result of the previous experiment. Even though the second experiment necessarily and intentionally involves far fewer simulations than the first, the disadvantage of the method is that, in the second experiment, the entire circuit is simulated using SPICE; this severely limits the size of circuits that may be analyzed in practice. A hierarchical method was proposed by [SI. It is a method of yield estimation applied to cascaded blocks having an input- output relation that may be described by an analytic transfer function. Parameters are mapped between various levels of hierarchy using these equations. Use of a hierarchical approach resulted in a gain of efficiency of typically one order of magnitude in estimating yield. The drawback of the method is that it assumes that an a priori analytical expression exists relating device-level parameters and performance parameters, and therefore lacks generality. An approach based on design- rule equations was proposed by [9]. Operational amplifier cells are partitioned into subcells whose large-signal and small- signal performance can be described by analytic design-rule equations. A process simulator maps the variations of the statistically independent process parameters onto the param- eters required in the analytical equations giving the statistical 0278-0070/96$05,00 zyxwvut 0 1996 IEEE