Parametric Yield in FPGAs Due to Within-die Delay Variations: A Quantitative Analysis Pete Sedcole and Peter Y. K. Cheung Dept. Electrical and Electronic Engineering, Imperial College London, UK {pete.sedcole,p.cheung}@imperial.ac.uk ABSTRACT Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re- configurability of Field-Programmable Gate Arrays presents the opportunity to compensate for within-die delay variabil- ity. This paper presents three reconfiguration-based strate- gies for compensating within-die stochastic delay variabil- ity in FPGAs: reconfiguring the entire FPGA, relocating subcircuits within an FPGA, and reconfiguring signal paths within a design. The yield of each strategy is analysed and compared with worst-case design and statistical static tim- ing analysis (SSTA). It is demonstrated that significant im- provements in circuit yield and timing are possible using SSTA alone, and these improvements can be enhanced by employing reconfiguration-based techniques. Categories and Subject Descriptors B.6.1 [Integrated Circuits]: Design Styles—Logic arrays ; B.7.1 [Integrated Circuits]: Types and Design Styles— Advanced technologies General Terms Performance, Theory Keywords Delay, FPGA, modelling, process variation, reconfiguration, statistical theory, within-die variability, yield 1. INTRODUCTION Variations in process parameters during semiconductor fabrication are manifested in the variability of the per- formance of the resulting integrated circuits. Historically, performance parameters have varied from wafer to wafer or lot to lot. At-speed testing techniques combined with speed-binning has been employed to partially compensate Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. FPGA’07, February 18–20, 2007, Monterey, California, USA. Copyright 2007 ACM 978-1-59593-600-4/07/0002 ...$5.00. for variations in propagation delay between dice. In deep- submicron technology nodes, variations in transistor and wire parameters within the same die are expected to be- come significant [15, 18]. The parametric difference between two nominally identical features on the same die is partly stochastic and partly correlated, with the correlation de- pending on physical locality. Importantly, several sources of stochastic variation are intrinsic to the materials used in fabrication [3, 2]. Stochastic variability cannot therefore be eliminated by improving the fabrication process, and is in fact predicted to increase relative to other sources of vari- ability [15]. Like other high-performance integrated circuits, Field- Programmable Gate Arrays (FPGAs) are affected by para- metric variability. However, their reconfigurability gives FP- GAs two distinct advantages over ASIC solutions. Firstly, the actual performance of each FPGA can be measured and characterised by configuring the device with Built-In Self- Test (BIST) circuits. Secondly, in theory it is possible to compensate for, or even make use of, the variations in per- formance by adapting the application circuit based on the measured parameters of the target FPGA (see for exam- ple [8]). There are a number of ways in which a circuit could be made adaptive to within-FPGA variations in performance. The approach taken has a significant impact on the develop- ment of parametric test techniques, circuit design methods and tools. It is crucially important to quantify the perfor- mance improvement a given approach is expected to provide. The novel contributions of this paper are: (a) a discussion of generalised reconfiguration-based strategies for variation- adaptive circuits in FPGAs (in Section 3), (b) analytical models based on the statistical theory underlying each strat- egy, as well as statistical static timing analysis and worst- case design (Section 4), (c) comparisons of the various tech- niques using the models, verified by Monte Carlo simulations (Section 5). This fundamental theoretical research provides a basis for exploration of variability-adaption techniques. 2. BACKGROUND The manufacture of high-performance digital integrated circuits requires rigorous control over many process vari- ables, each of which influence propagation delay to a differ- ent extent [15]. Deviations from nominal values in process variables can be systematic or stochastic [4, 10]. The ef- fect can be localised to a few transistors, a die, a wafer or an entire lot. Systematic variations induce a shift in circuit parameters, sources of which include, for example, mask er- 178