IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 11, NOVEMBER 1997 1625 A 533-MHz BiCMOS Superscalar RISC Microprocessor Cliff A. Maier, Member, IEEE, James A. Markevitch, Member, IEEE, Cheryl Senter Brashears, Tim Sippel, Member, IEEE, Earl T. Cohen, Jim Blomgren, James G. Ballard, Jay Pattin, Viki Moldenhauer, Jeffrey A. Thomas, Member, IEEE, and George Taylor Abstract—This 533-MHz BiCMOS very large scale integration (VLSI) implementation of the PowerPC architecture contains three pipelines and a large on-chip secondary cache to achieve a peak performance of 1600 MIPS. The 15 mm 10 mm die contains 2.7M transistors (2M CMOS and 0.7M bipolar) and dissipates less than 85 W. The die is fabricated in a six-level metal, 0.5- m BiCMOS process and requires 3.6 and 2.1 V power supplies. Index Terms—BiCMOS integrated circuits, bipolar digital in- tegrated circuits, emitter coupled logic, microprocessors. I. INTRODUCTION A THREE-WAY superscalar microprocessor chip imple- menting the PowerPC Architecture [1], [2] has been designed to operate at 533 MHz by taking advantage of an advanced BiCMOS process and through innovative design techniques. The processor is designed to be compatible with existing air-cooled desk-side systems and is fully compatible with the PowerPC 60 bus standard [3], supporting bus speeds up to 100 MHz. The chip contains 2.7M transistors on a 15 mm 10 mm die fabricated with a 0.5- m BiCMOS tech- nology providing five global and one local interconnect layer (Table I). The estimated SPECint_base95 and SPECfp_base95 for the chip, assuming a 1-MB off-chip cache and a 66-MHz bus, are 12 and 10, respectively. The processor’s high speed was achieved by devising a microarchitecture designed with attention to the capabilities of the process. Manuscript received April 17, 1997; revised July 31, 1997. C. A. Maier and C. Senter Brashears were with Exponential Technology, San Jose, CA 95131 USA. They are now with AMD, Sunnyvale, CA 94088 USA. J. A. Markevitch was with Exponential Technology, San Jose, CA 95131 USA. He is now with Evergreen Technology, Palo Alto, CA 94301 USA. T. Sippel was with Exponential Technology, San Jose, CA 95131 USA. He is now with Alchemy Designs, Sunnyvale, CA 94087 USA. E. T. Cohen was with Exponential Technology, San Jose, CA 95131 USA. He is now with BiT Microsystems, Fremont, CA 94538 USA. J. Blomgren was with Exponential Technology, San Jose, CA 95131 USA. He is now with EVSX, Austin, TX 78735 USA. J. G. Ballard was with Exponential Technology, San Jose, CA 95131 USA. He is now with Sun Microsystems, Mountain View, CA 94043 USA. J. Pattin was with Exponential Technology, San Jose, CA 95131 USA. He is now with Epigram, Palo Alto, CA 94301 USA. V. Moldenhauer was with Exponential Technology, San Jose, CA 95131 USA. She is now with Philips Electronics, Sunnyvale, CA 94088 USA. J. A. Thomas was with Exponential Technology, San Jose, CA 95131 USA. He is now with DEC, Palo Alto, CA 94301 USA. G. Taylor was with Exponential Technology, San Jose, CA 95131 USA. He is now a consultant in Los Altos, CA 94024 USA. Publisher Item Identifier S 0018-9200(97)08028-1. TABLE I PROCESS AND CHIP FEATURES The three-way superscalar microarchitecture issues one inte- ger or floating-point, one load/store, and one branch instruction in parallel per cycle. Two-to-three way superscalar is an architectural “sweet spot”: enough hardware parallelism to be effective without requiring complex, out-of-order execution. All logic circuits are implemented in three-level emitter coupled logic (ECL) with input ORing, allowing extremely complex gates. Only RAM structures were implemented with CMOS circuits. Each gate may contain an arbitrary number of emitter followers, having inverted or noninverted inputs, and having outputs on any combination of the three voltage levels. Since several circuit core and emitter follower power levels are available, the cell library is extremely large. Advanced design tools allow most cells to be automatically generated, providing layout as well as timing information for use in the design process. All single-ported RAM circuits are implemented with 6T CMOS cells and bipolar word line drivers and sense amps, with additional access devices for multiported RAM structures. 0018–9200/97$10.00  1997 IEEE