Hindawi Publishing Corporation International Journal of Reconfgurable Computing Volume 2013, Article ID 942021, 2 pages http://dx.doi.org/10.1155/2013/942021 Editorial Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011) Massimo Conti, 1 Elmar Melcher, 2 Jürgen Becker, 3 Alisson Brito, 4 and Oliver Sander 3 1 Dipartimento di Ingegneria dell’Informazione, Universit` a Politecnica delle Marche, Via Brecce Bianche, Ancona, Italy 2 Centro de Engenharia El´ etrica e Inform´ atica, Universidade Federal de Campina Grande, Brazil 3 Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), 76131 Karlsruhe, Germany 4 Centro de Informatica, Universidade Federal da Paraiba, Jo˜ ao Pessoa, Brazil Correspondence should be addressed to Massimo Conti; m.conti@univpm.it Received 13 May 2013; Accepted 13 May 2013 Copyright © 2013 Massimo Conti et al. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. SBCCI is an international forum dedicated to Integrated Circuits and Systems Design, Test and CAD, held annually in Brazil, copromoted by SBC, SBMicro, IEEE CAS, ACM SIGDA, and IFIP WG 10.5. Te 24th edition of the Sympo- sium on Integrated Circuits and Systems Design (SBCCI) was held in Jo˜ ao Pessoa, PB, Brazil, from August 30 to September 2, 2011. Track 2.1 of SBCCI 2011 was dedicated to Reconfgurable Computing. Some of the papers of this track have been selected for this special issue. Tis special issue presents some of the latest develop- ments in the area of design, specifcation, and modeling lan- guages and applications of reconfgurable computing; recon- fgurable architectures and novel applications of FPGAs; hardware-sofware codesign and coverifcation; emulation and prototyping techniques. Ten articles are in this issue. Te main disadvantages of the reconfgurable approaches are still the costs in area and power consumption. In “Hon- eyComb: an application-driven online adaptive reconfgurable hardware architecture,” A. Tomas et al. present a solution for application driven adaptation of a reconfgurable architecture at register transfer level to reduce the resource requirements and power consumption while keeping the fexibility and performance for a predefned set of applications. A prototype chip of this architecture designed in 90 nm standard cell technology manufactured by TSMC is presented. Multiprocessor system-on-chip (MPSoC) security is becoming an important requirement. Te challenge is to provide MPSoC security that makes possible a trustworthy system that meets the performance and security requirements of all the applications. Te network-on-chip (NoC) can be used to efciently incorporate security. In “QoSS hierarchical NoC-based architecture for MPSoC dynamic protection,” J. Sepulveda et al. propose the implementation of Quality of Security Service to overcome present MPSoC vulnerabilities. Te paper presents the implementation of a layered dynamic security NoC architecture to overcome actual MPSoC vulner- abilities. Networked multiprocessor system-on-chips are used to implement novel embedded applications characterized by increasing requirements on processing performance as well as the demand for communication between several devices. Such systems require a detailed exploration on both, architec- tures and system design. In “Efcient execution of networked MPSoC models by exploiting multiple platform levels,” C. Roth et al. present a methodology that embeds previous work into a simulation platform, which facilitates efcient execution of cross-domain simulation models on diferent abstraction levels. In “Open systemC simulator with support for power gating design,” G. S. Silveira et al. present an open source SystemC simulator with support to Power Gating design. Tis sim- ulator is an alternative to assist the functional verifcation accomplishment of systems modeled in RTL. Te possibility of controlling the retention and isolation of Power Gated Functional Block is presented turning the simulations more stable and accurate.