Abstract— A low power and high performance 1-bit full adder cell is proposed. The 8T Full Adder technique has been used for the generation of XOR function. Twelve state-of-the- art 1-bit full adders and one proposed full adder are simulated with HSPICE using 0.18μm CMOS Technology at 1.8V supply voltage. By optimizing the transistor size in each stage the power and delay are minimized. The results of post-layout simulation compared to similar reported ones illustrate significant improvement. Simulation results show great improvement in terms of Power-Delay-Product (PDP). The power consumption of this adder is 200nw. Index Terms—Full Adder, Low Power, CMOS, Delay I. INTRODUCTION NTEGER addition forms the basis of digital computer systems. Addition was found to be the most frequently encountered operation among a set of real time digital signal processing benchmarks in [1]. About 72% of the instructions of a prototype RISC machine, DLX resulted in addition/subtraction operations [2]. A study of the operations performed by an ARM processor’s ALU revealed that additions constituted nearly 80% [3]. Historically, VLSI designers have used speed as the performance metric. High gains, in terms of performance and silicon area, have been made for Digital circuits. In general, small area and high performance are two conflicting constraints [4]. The power consumed for any given function in CMOS circuit must be reduced for either of the two different reasons: One of these reasons is to reduce heat dissipation in order to allow a large density of functions to be incorporated on an IC chip. Any amount of power dissipation is worthwhile as long as it doesn’t degrade overall circuit performance. The other reason is to save energy in battery operated instruments same as electronic watches where average power is in microwatts In CMOS circuits there are three types of power dissipation namely, the dynamic power dissipation, the short circuit power dissipation and the leakage power dissipation [5]. The average dynamic power dissipation of the CMOS logic gate, can be calculated from the energy required to charge down the total output load capacitance to ground Manuscript received November 30, 2011; revised February10, 2012. Amin Bazzazi is with Computer Engineering Department, Gorgan Branch, Islamic Azad University, Gorgan, Iran. (E-mail: bazzazi@ gorganiau.ac.ir). Alireza Mahini is with Computer Engineering Department, Gorgan Branch, Islamic Azad University, Gorgan, Iran. (E-mail: mahini@ gorganiau.ac.ir). Jelveh jelini is with Computer Engineering Department, Gorgan Branch, Islamic Azad University, Gorgan, Iran. level and charge up the output node to the V DD driven by a periodic input voltage waveform with ideally zero rise and fall times. The total output of the dynamic power consumption is proportional to switching activity, capacitive loading and the square of the supply voltage [6]. The structure of the rest of this paper is organized as follows: Section II reviews twelve states of the full adder cells. In section III the Implementation of full adder with the 8T Technique is described. The simulation results are shown in section IV. Finally, section V contains the conclusion. II. REVIEW OF TWELVE STATE OF THE ART FULL ADDER CELLS There are different types of CMOS full adder. This section reviewed the twelve state-of-the-art 1-bit full adders. This proposed cell is compared with them. Twelve state of the art full adder cells are: 10T, 14T, CPL, TFA, TG CMOS, C 2 MOS, Hybrid, Bridge, FA24T, N-Cell, DPL and Mod2f. The first full adder structure in this section is 10T. It has only 10 transistors. The number of transistors is the advantage of this cell which leads to better performance and less silicon area. However poor driving capability and non full swing nodes are the serious problems of this full adder cell. The power consumption of this structure is 1.13μw.It is shown in fig. 1(a). The 14T adder with 14 transistors consumes considerably less power in the order of microwatts and has higher speed. The 14T adder reduces threshold loss problem compared to the previous different types of transistor adders. In future, this kind of low power and high speed adder cell will be used in designing the digital FIR filter. The power consumption of this structure is 6.4μw. It is shown in fig. 1(b) [7]. The Complementary Pass-transistor Logic (CPL) full adder is shown in figure 1(c). This is contains the 18 transistors that based on NMOS pass-transistor network. This causes low input capacitance and high speed operation. Due to less output voltage swing that is the result of one Vt loss in the output, CPL consumes less power than standard static CMOS circuits. The power consumption of this structure is 2.5μw [7]. A Transmission Function Full Adder (TFA) based on the transmission function theory is shown in figure 1(d). It has 16 transistors. The power consumption of this structure is 12μw. A Transmission- Gate Adder (TGA) is shown in figure 1(e). Transmission gate logic circuit is a special kind of pass-transistor logic circuit. It is built by connecting a Low Power Full Adder Using 8T Structure Amin Bazzazi, Member, IAENG, Alireza Mahini and Jelveh Jelini I Proceedings of the International MultiConference of Engineers and Computer Scientists 2012 Vol II, IMECS 2012, March 14 - 16, 2012, Hong Kong ISBN: 978-988-19251-9-0 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online) IMECS 2012