Design and Evaluation of a Delay-Based FPGA Physically Unclonable Function Aaron Mills, Sudhanshu Vyas, Michael Patterson, Christopher Sabotta, Phillip Jones, Joseph Zambreno Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA Email: {ajmills, spvyas, mjpatter, csabotta, phjones, zambreno}@iastate.edu Abstract—A new Physically Unclonable Function (PUF) vari- ant was developed on an FPGA, and its quality evaluated. It is conceptually similar to PUFs developed using standard SRAM cells, except it utilizes general FPGA reconfigurable fabric, which offers several advantages. Comparison between our approach and other PUF designs indicates that our design is competitive in terms of repeatability within a given instance, and uniqueness between instances. The design can also be tuned to achieve desired response characteristics which broadens the potential range of applications. I. I NTRODUCTION A PUF is a device whose transfer function exploits physical phenomena in a way that cannot be replicated, even if the full design is known. It is also referred to as a physical one- way hash function when implemented in a challenge-response framework. PUFs reduce the ability of attackers to circumvent security mechanisms, as these mechanisms are implemented in tamper-resistant hardware [1, 2] rather than software. The devices are unclonable in the sense that, although they may be physically copied, this provides no advantage to an attacker, because each copy will behave differently. A variety of PUF designs have appeared over the past decade–roughly one each year since 2000 [3]. The most well- known delay-based PUFs are SRAM [4, 5], Butterfly [6], Ring Oscillator (RO) [7, 8], and Arbiter [9, 10] and the FPGA- specific Anderson PUF [11]. A more thorough survey that includes some non-delay-type PUFs appears in [12]. The PUF designed for this paper is a delay-type PUF that inherits the SRAM and Butterfly PUFs’ properties. Briefly, compared to the most popular designs, the one proposed: • Uses FPGA reconfigurable fabric, making testing easier than for SRAM PUFs. The circuit can be reset without requiring the whole device to be reset. • Is simpler than the non-linear Arbiter PUFs. In addition, unlike the arbiter PUF there have been no known model- building attack against PUFs which are based on inde- pendent cells. • Intuitively has a lower power requirement than the RO PUF, since it does not oscillate. A disadvantage is size: an n-bit response requires at least n cells. Additionally in their raw form this kind of PUF tends to suffer from a slightly higher-than-average level of noisiness. II. DESIGN AND I MPLEMENTATION A. Principle of Operation A memory-type PUF uses a small cell whose single-bit value is not known until it has stabilized after reset. For example, in Fig. 1a, if both switches are initially closed, then the capacitors at Q1 and Q2 are both charged. Then at t=0, Q1 Q2 VDD VDD R1 R2 (a) Conceptual Q Q SET CLR D 0 1 1 0 ‘1’ ‘1’ rst Q1 Q2 LUT LUT clk (b) Logical Fig. 1: PUF Design the switches are opened and the circuit resolves to a stable state which depends on the delay through the inverter and interconnects, as well as the switching threshold of the logic. If route R1 has a shorter delay, it will remain at logical 1 and force Q2 to logical 0. If route R2 has a shorter delay, it will remain at logical 1 and force Q1 to logical 0. Thus Q1 and Q2 will always resolve to opposing values, but which has which value depends on the physical properties of the hardware. The PUF design is shown in Fig. 1b. The switches are replaced by combinational logic implemented in LUTs. The function of the PUF based on the delay of a net d N can be described as d N = d S + d R + d NOISE . d S represents the static delay estimated by the design tool. d R is a random variable representing the uncertainty in net delay due to process variation. Finally, d NOISE is a dynamic random variable representing the effects of temperature and voltage variation as well as interaction between circuits. Both d R and d NOISE may be either negative or positive. Next, we can characterize the delay of the two nets, Q1 and Q2. Both d L1 and d L2 are additional random variables representing the delay through the two LUTs employed by a cell to create the necessary logic. They are always positive. d q1 = d L1 +(d Sq1 + d Rq1 + d NOISEq1 ) (1) d q2 = d L2 +(d Sq2 + d Sq2 + d NOISEq2 ) (2) Ideally, the quantity Δd S =(d Sq1 − d Sq2 ) should be 0 so that the effect of the random LUT and route delay components dominate. The difference between the delay of the routes, Δd (5), dictates the circuit outcome. Finally, the PUF can be described by a pair of piecewise functions depending on Δd. Q1=  1 :Δd< 0 0 :Δd> 0 (4a) Q2=  1 :Δd> 0 0 :Δd< 0 (4b)