Effect of ITC on the Characteristics of Junctionless Nanowire Transistor(JLNWT) for Future ULSI Applications:Semianalytical Modeling Approach Yogesh Pratap, M. Gupta Semiconductor Device Research Laboratory Department of Electronics Science University of Delhi South Campus New Delhi- 110020, India Email: yogi.pratap87@gmail.com , mridula@south.du.ac.in Subhasis Haldar Department of Physics Motilal Nehru College, University of Delhi New Delhi- 110021, India Email: subhasis_haldar@rediffmail.com R. S Gupta Department of E&C Maharaja Agrasen Institute of Technology Delhi- 110086, India Email: rsgupta1943@gmail.com Abstract— Junctionless Nanowire Transistor (JLNWT) is now being considered one of the most attractive and deserving candidate for future ULSI applications due to its high current driving capability and better SCEs immunity. In this paper, a semi-analytical subthreshold current model has been developed for short channel JLNWT including interface trap charges (ITC) density. This paper explores the electrical performance degradation of JLNWT due to fixed/interface trap charges. Effect of extension, position, density and polarity of interface trap charges are discussed in terms of change in electrical parameters of JLNWT such as central potential, threshold voltage roll-off, subthreshold slope, drain induced barrier lowering and subthreshold current. Impact of technology variation such as channel length, silicon film radius has been carried out in the details. Model verified by using ATLAS 3D device simulator. Results reveal that ITC significantly affects the sensitivity of Junctionless NWT and is more noxious at subthreshold region. Keywords—Junctionless Nanowire Tranistor(JLNWT), Short Channel Efeects(SCEs), Interface Trap Charge Density(ITCD), Gate All Around (GAA) I. INTRODUCTION As the transistor device dimensions are approaching near to the semiconductor technology roadmap, the short channel effects (SCEs) become very extensive in extremely scaled devices and they significantly degrade the overall device performance. The formation of ultra-sharp Source/Drain junctions becomes very complex since it requires extremely precise doping and thermal condition [1], [2]. In nano-scale devices the sharp Source/Drain junctions make it hard to accurately predict the device performances [3]. Therefore, for future Ultra Large Scale integration (ULSI) applications, more and more fundamental device level changes become mandatory. Recently Junctionless Transistor [4] has been proposed as a novel structure to make a breakthrough for junction induced design issues. The junctionless transistors are uniformly heavily doped throughout the source, channel and drain region and there is no formation of junctions thereby eliminating the problem of the diffusion of the impurities. Various performance analyses [1-6] have been carried out and demonstrated that junctionless nanowire transistor have better analog/RF performance, superior scaling capability, significantly improved electrical characteristics, simple fabrication processes and are less susceptible to short channel effects than the classical inversion-mode(junction-based) nanowire transistor. Apart from short channel immunity, long channel reliability is a major concern for heavily scaled devices. Interface trap charges created during manufacture of a transistor at silicon (Si) and oxide (SiO 2 ) interface degrades the device performance [7] and it can be serious device reliability issues. These interface traps are induced due to: (1) process induced damage [8], (2) stress induced damage [9], (3) radiation induced damage [10] and (4) hot carrier induced damage [11]. A lot of research work has been carried out to study the device electrical performance degradation due to interface trap charges in inversion mode (junction-based) transistor [12-13]. But there is a need to estimate the electrical performance degradation in Junctionless transistor. Further the use of junctionless nanowire transistor in the circuits, it is necessary to develop the physics based and feasible device model [14]. Recently, Gnudi et. al, has proposed a semi-analytical model for junctionless double gate MOSFET which is more accurate than the previous available models[15]. But there is no appropriate model has been developed for short channel junctionless gate all around (GAA) MOSFET. The aim of this paper is to study the electrical performance degradation of GAA junctionless nanowire transistor (JLNWT) due to interface trap charges by employing the semi-analytical modeling approach. This model includes the effect Source/Drain depletion region along with the ITC density. The quantum effects are not considered in the present analysis as the quantum mechanical effects are dominant for silicon film thicknesses smaller than 5 nm and for a channel length below 10 nm [16]. Here silicon film thickness and channel length is taken to be 10 and 20 nm respectively. 978-1-4799-2275-8/13/$31.00 ©2013 IEEE 2013 Annual IEEE India Conference (INDICON)