Design of an Open-Source, NoC-based MPSoC: Open-Scale Remi Busseuil, Lyonel Barthe, Gabriel Marchesan Almeida, Gilles Sassatelli, Pascal Benoit, Michel Robert, Lionel Torres LIRMM, UMR 5506, CNRS University of Montpellier 2 161, rue Ada, 34085 Montpellier Cedex 5, France Email: {firstname.lastname}@lirmm.fr I. I NTRODUCTION The increasing complexity of application and higher per- formance demand make Multi-Processors System on Chip (MPSoC) one valuable alternative for dealing with nowadays requirements. Single core CPUs are no longer sufficient to provide the performance to power ratio specified in new embedded system standards. Technology scaling of sub-micronic manufacturing process leads to a change in the design constraints such as area, power and complexity optimization. The density of a digital system is not the main issue, while reliability and power consumption become the most important aspects to be considered in the design specifications. In this context, multi-core designs can handle both performance and complexity issues once they can be easily scaled-up. One of the key-point regarding system performance con- cerns communication issues. Many-cores structures imply fine communication development to deal with the concurrent ac- cesses of shared resources. In this direction, classical bus architectures do not scale well once new nodes are added to the system. In opposite, NoC architectures are well-known solutions due to their scalability and are widely used for hard- ware interconnecting on large architectures. Such systems have gathered much attention from industry [1] [2] [3]. However, to the best of our knowledgement, synthesizable NoC-based MPSoC architectures with operating system support are not available under public domain. The need of rapid prototyping and software/hardware co-designs validation make the use of open-source NoC-based MPSoC architectures particularly attractive. II. ARCHITECTURE DESCRIPTION A. MPSoC Overview The key motivation for building Open-Scale architecture concerns scalability; the architecture here presented is built of a distributed memory/message passing approach that uses a 2d-mesh NoC for connecting different PEs. For this reason, the PE is called NPU, for Network Processing Unit [4]. The NPU structure is depicted in Fig. 1 that provides a general overview of the NPU internal architecture. A NPU is composed by a microprocessor, an embedded RAM, an interrupt controller, a timer, a UART and a router. !"#$"%&'()" +,-#$.&'()" #/01 2"$,"! 3.# !"# -3%"$$0/% #.3%$.''"$ %-,"$ '4 -#(#2" '4 5#(#2" 3.# -3%"$6(#" $(, 7-!2&.3" &0! Fig. 1. A Network Processing Unit The IP cores are interconnected through a Wishbone v4 bus [5]. The timer is a 32-bit counter that can generate an interruption according to a configurable time window. The interrupt controller can handle up to 8 interruptions and manages masking, arming, and polling. The NoC router is a small XY router based on Hermes project [6]. B. Processor The processor implemented in Open-Scale is the Secret- Blaze [7], a highly configurable open-source RISC soft-core processor developed by our research group. It implements the MicroBlaze instruction set architecture with a MIPS five- stage pipeline, where most of the instructions requires one clock cycle to be executed, achieving high-performance at low cost. The development of the processor was mainly conducted keeping a modular approach, not only to ensure reliability and efficiency across the whole design, but also to provide better design reuse opportunities in various research and educational projects. The flexibility is one of the driving aspects of the Secret- Blaze design. On the one hand, the core provides several optional logical and integer instructions such as multiplication, division, and pattern operations, which balances computing performance and area cost to meet embedded system require- ments. On the other hand, the SecretBlaze is a MMU less processor with a simplified memory sub-system that offers