A Design of Small Area Vernier Based TDC with 10 ps resolution for Phase Difference Detection in ADPLL Application Muhammad Basim, Khuram Shehzad, Arash Hejazi, Deeksha Verma, Muhammad Asif, Qurat ul Ain, Imran Ali and Kang-Yoon Lee Department of Electrical and Computer Engineering, Sungkyunkwan University {basim,khuram1698,arash,deeksha27,m.asif,quratulain,imran.ali,klee}@skku.edu Abstract Several architectures are used to detect phase difference between the reference and output oscillations of an all-digital phase-locked loop (ADPLL). A time-to-digital converter (TDC) is used to accomplish this task by converting the phase difference in digital format. This paper describes the performance and architecture of a low area and high resolution Vernier based TDC using arbiter. The small area delay cells and arbiter ensure high resolution of 10 ps. Two delay cell chains having difference in delays (~10 ps) are implemented for the reference and the output of ADPLL. The difference in delay cells can be controlled through Delay Locked Loop (DLL), including changes due to PVT variations. The proposed TDC is implemented in 180 nm CMOS technology with 0.0019 mm 2 area. The input frequency is 2 GHz and supply voltage is 1.8 V. The simulation results of Vernier delay line (VDL) TDC proves the conservation time of 10 ps. Keywords: ADPLL, digital phase-locked loop (DPLL), time-to-digital converter (TDC), Vernier delay line (VDL). Introduction Recently, TDCs gained high interest due to its high resolution in the implementation of All Digital Phase Lock Loop, time of flight (TOF) range finder, jitter measurement, biomedical imaging and LiDAR. The device used for the measuring time interval and then converting this time interval into digital is known as TDC. By using high time resolution circuit, a high accuracy phase locked loop (PLL) circuit can be achieved. Also, to increase the data rate of a serial link, a high time resolution and higher number of bits circuit is required. By allowing high reference frequency, the phase noise is improved as compared to other architectures. The TDC quantizes time interval between stop and start signals and represents with a digital code. The key element of digital phase-locked loop is high resolution CMOS TDC. The counter is the simplest TDC in time domain with reasonable resolution of time signal which can be digitized by counter. However, the frequency of reference clock would be increased when the TDC resolution requirement increases to a few picoseconds. Vernier based TDC In this paper a Vernier based TDC is proposed using arbiter. The way to improve the time resolution performance is shown in the figure 1. Time resolution is given by equation 1 as follows:   = ∆ = 2−1 (1) Where τ1 and τ2 are the propagation delay of the buffers which is used for slow and fast delay chain. In the proposed architecture, τ1 and τ2 re 92 ps and 102 ps respectively. This means the final resolution is 10 ps. Figure 2 is the timing diagram for resolution of start and stop signals which are delayed by buffers. The time resolution of Vernier based TDC is almost 5 time better than other traditional TDCs. Table 1 shows the comparison between the performance and time resolution of Vernier based TDC with other TDC structures. The actual resolution of a TDC is effective which have better performance in fine time resolution and wide phase detection range [1]. The rotation of leading and triggering signals occur until the arbiter shows its judgment that the leading signal caught the triggering signal. The number of delay stages is reduced by the reuse of delay chain. Without any affect, the measured maximum time interval is the dynamic range of a TDC. Since the system detection range of LiDAR experiment needs over