FPGA Based Capacitive Touch Pad/Interface Radovan Stojanović, Nedjeljko Lekić, Zoran Mijanović and Jovan Kovačević Faculty of Electrical Engineering University of Montenegro Podgorica, Montenegro stox@ac.me Abstract — This paper reports a sensing principle and FPGA design of a capacitive touch pad/interface where the sensing pad is connected to the I/O pin via an external resistor. The circuit transforms the change in pad capacitance into voltage amplitude during charging, discharging and sharing phases. By using multiple pins and resistors, a multipad system is achieved. The sensing algorithm is implemented in VHDL code. The read-out cycle is parallel and short, what results in a high noise immunity in low frequency range. The silicon/hardware requirements are minimal. The interface can be easily embedded into a system-on- chip and used for human-machine, bio-chemical and mechanical sensor interfacing. Keywords— FPGA; capacitive pad; sensor; touch interface I. INTRODUCTION The capacitive sensors have long history of use in industrial measurements, but only during the last two decades they started to make inroads into human-computer interaction. The expansion of multifunctional and multimedia digital devices and gadgets, such as smart phones, iPads and different mobile and desktop instruments have opened huge opportunities for commercialization and further development of these types of interaction. In the open literature and available to us applications different capacitive sensing techniques can be identified: oscillator-based, resistor-based, approaches based on switched capacitors and programmable current sources etc. [1, 2]. The read-out circuits are usually implemented in microcontroller [3, 4] or ASSP (Application Specific Standard Products) chips [5]. Essentially, none of the elaborated approaches and systems can fully and satisfactorily answer main requirements of today's and future capacitive sensing interfaces: i) serving almost infinite number of sensor pads; ii) reading pads quickly; iii) achieving high noise immunity; iv) embedding interface in same chip with the rest of digital system and v) reaching a competitive cost. FPGA (Field Programmable Gate Arrays) technology with full parallelism, huge capacity of digital circuits, high operating speed, on-chip signal processing possibilities and affordable price, shows a potential to solve some of the above issues. This paper presents an FPGA based methodology for capacitive sensing which includes minimal number of external components and appears to be suitable for human-machine, bio-chemical and mechanical multi sensor interface. II. SENSING PRINCIPLE AND SYSTEM DESIGN A. Sensing Principle In single-touch configuration the sensing pad is connected to the bidirectional FPGA pin Pn via resistance R, Fig. 1. The direction of pin, input or outpud, is determined by DIR register, while the input state is read by IN register. C p is a pin capacitance and for FPGAs has value of about 4pF. C b is body-ground capacitance, typically in the range 100pF-150 pF, but can be as high as 400pF. C x0 and C x1 are the capacitances of untouched and touched pad, respectively. Usually, C b >>C x1 , expressing the equivalent capacitance pad- finger-ground system as C x ≈C x0 +C x1 . C xo has the value of 6.5pF for D=10m, while C x1 decreases from 7pF-1.5pF for 0.1mm<d x1 <1mm. Fig. 1. FPGA based capacitive pad/interface The sensing process starts with “CHARGE” phase, Fig. 2, by setting logical “1” (3.3V) to the pin P n for time t c =0.75us- 2us, long enough to charge C p and C x to the values V 1 =V 2 =3.3V. Dashed line indicates situation for increased value of Cx, pad touched. During the “DISCHARGE” phase, C p discharges totally, because of V 1 =0V, while V 2 declines by time constant RC x reaching the end value V 2 (t d ) after the discharging time t d . t d may be chosen between 200ns-750ns.