A Built-In Self-Test and Self-Diagnosis Scheme for Embedded SRAM Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng*, Kevin Chiu*, and Hsiao-Ping Lin* Lab. for Reliable Computing Department of Electrical Engineering National Tsing Hua University Hsinchu, Taiwan "Faraday Technology Corp. Hsinchu, Taiwan Abstract Embedded memory test and diagnosis is becoming an im- portant issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It sup- ports manufacturing test as well as diagnosis for design ver- ification and yield improvement. The proposed BISD cir- cuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our ex- perimental results show that the BISD hardware overhead is about 2.4% for a typical 128Kb SRAM and only 0.65% for a 2Mb SRAM. 1. Introduction System-on-chip (SOC) designs are becoming an ob- servable trend as VLSI technologies continue to innovate. Multi-billion-transistor chips are not too far away. In order to handle the design complexity and keep a reasonable turn- around time, reusable cores or intellectual properties (IPS) are being used in many SOC applications. However, there still are many unsolved SOC design issues, among them the core tesddiagnosis problem has already posed great chal- lenges to the industry as well as the research community [ 11. We will focus on memory core test and diagnosis in this pa- per. Direct access of cores is one of the major problems so far as testing and diagnosis is concerned. The available bandwidth between the primary I/O pins of the system chip and the embedded core usually is very limited, so to deliver test patterns and observe test results efficiently is difficult, and normally requires the use of some kind of design-for- testability (DFT) methodology. Furthermore, mature tool support in this respect is not available so far. For memory cores, however, built-in self-test (BIST) is a promising ap- proach to attacking the problem. With only a small area overhead, BIST provides at-speed, high-bandwidth access to the memory core under test. It requires only a small bandwidth for the low-cost external logic tester (instead of the expensive high-performance memory tester) to apply test commands and to inspect the final results. It is now widely agreed that BIST is suitable for embedded DRAMS and SRAMs in general [2-51. However, BIST is not ready to replace memory testers yet. High-density and high-capacity memory cores are more vulnerable to physical defects than logic cores. In addition to testing the embedded memories using March-based al- gorithms [5-71, diagnosis of the fault sites and subsequent repair by redundant word- and/or bit-lines to increase the yield is necessary for large cores. Therefore, built-in self- diagnosis (BISD), built-in redundancy analysis (BIRA), and even build-in self-repair (BISR) methodologies are becom- ing inevitable, so far as overall test cost is concerned [8,9]. In this paper, we present a programmable B E D (includ- ing BIST) design for embedded SRAM. In association with the BISD design, we also have developed a diagnosis sys- tem. Embedded SRAMs are the most widely used cores in almost all SOC applications, such as computer peripher- als, consumer electronics, network products, and multime- dia products. The proposed BISD core has a fault-location mode that supports laser repair, and an on-line programming mode for custom test commands. An efficient test algorithm was built-in to cover all stuck-at, transition, inversion cou- pling, state coupling, idempotent coupling, and stuck-open faults of the word-oriented memory cores. The default al- gorithm, called March-CW, is one of the cocktail-March al- gorithms that we developed earlier for efficient testing of word-oriented memories [ 10,11]. The on-line programming mode makes it possible for the user to apply more sophisti- cated diagnosis algorithms. Upon receiving the fault loca- 1081-7735/00 $10.00 0 2000 IEEE 45