1 Abstract The use of multiprocessor systems is the main method for providing a high computational power. Multistage interconnection networks (MINs) are widely used to connect processors and memory modules in multiprocessor systems. Therefore, the design of an efficient MIN is an essential requirement for the development of multiprocessor systems. In addition, a critical parameter for any efficient interconnection network is reliability. However, the problem in the way of designing high-reliable interconnection networks is high hardware cost. To solve this problem, contribution of this paper is to propose a new approach to improve the reliability of the MINs, called the rearranging links. The proposed approach is implemented on two common MINs namely extra-stage shuffle- exchange network (SEN+) and augmented shuffle-exchange network (ASEN). Meticulous analysis of terminal reliability proves that the proposed approach is an efficient method to improve the reliability of MINs. In addition, performed cost analysis confirms that utilizing it leads to emerge cost-effective MINs. Keywords: Multiprocessor systems, Multistage interconnection network, Reliability, Cost-effectiveness, Reliability block diagrams 1. Introduction Trends in fast networks, distributed systems, and multiprocessor computers during the past decade show that parallelism is a perfect solution for high computational power [1, 2]. Parallel processors can be defined as a computer system that is made of multiple processors that are linked together by an interconnection network and the software required for the management of processors working together [3]. Consider a generic high-end parallel architecture. This system is shown in Fig. 1. Here, several processor nodes exist that an interconnection network provides the connection between them. This network is responsible for transferring data between the processor nodes. In this system, each node consists of three components: a (probably multi-core) processor (P), a share of the main memory (M), and a cache hierarchy (C). In addition, the connection between processor nodes and global interconnection network can be created by a network interface (NI). I/O devices such as disks are also other important components of this system. I/O devices are often connected to an I/O bus, which is interfaced to the memory in each processor node via the interconnection. Therefore, it can be argued that the three vital components of a multi-processor computer are processor, memory hierarchy, and interconnection network [4]. Fig. 1. Generic multiprocessor system with distributed memory. Therefore, multi-processor systems require efficient interconnection networks in order to achieve a desired level of performance. In this regard, the design of an efficient network is a necessary phase for the construction of high-  Corresponding author, Tel: +98 21 44 6000 46 Rearranging links: A Cost-Effective Approach to Improve the Reliability of Multistage Interconnection Networks Fathollah Bistouni 1 and Mohsen Jahanshahi 2 1 Department of Computer Engineering, Central Tehran Branch, Islamic Azad University, Tehran, Iran 2 Young Researchers and Elite Club, Central Tehran Branch, Islamic Azad University, Tehran, Iran fat.bistouni.eng@iauctb.ac.ir, mjahanshahi@iauctb.ac.ir