10 th International Conference on DEVELOPMENT AND APPLICATION SYSTEMS, Suceava, Romania, May 27-29, 2010 236 Abstract — This paper describes the digital systems synthesis based on direct mapping of Petri nets model into FPGA circuit. A design flow that includes the specification of the system using Synchronous Petri Nets, verification of the behavioral properties of the model, generation of the mathematical model of Hard Petri Nets (HPN), used for automatic generation of the AHDL code is described. The direct mapping approach avoids algorithmic complexity inherent in logic synthesis based on state encoding and substantially reduces the design time and cost. The method used for modeling and implementation of the digital systems was validated using MAX+PLUS II design environment. Index Terms — AHDL, digital system, direct mapping, FPGA, MAX+PLUS II, Hard Petri Nets. I. INTRODUCTION Advances in semiconductor technology over the last four decades have resulted in a nearly constant compound growth in transistor density of approximately 46% per year [1]. This remarkable achievement has not been matched by an equivalent increase in integrated circuit designer productivity, leading to a design gap as illustrated in Figure 1. Figure 1. The design productivity gap. The design gap represents the disparity between the transistors available to a designer and the ability to use them effectively in a design. Increases in productivity are limited by the spiraling system complexity engendered by increased transistor counts. Traditional design methods do not scale to match the increased complexity. On the other side, the growth of design productivity leading to a so called “verification crisis”. According to a Collett international study, the rate of first silicon success is steadily declining, dropping to 35% in 2003; 70% of re-spun designs contain functional bugs [2]. One of the ways to overcome this threat is through improving the productivity and efficiency of the design process, particularly by means of new synthesis approaches that can transform a behavioral specification into an adequate implementation. The use of Petri nets for the specification, analysis and synthesis of digital systems has proved very worthwhile. Petri nets are mathematically well founded and can be used to capture causality relations, concurrency of actions and conflicting conditions from digital systems in a natural and convenient way. It is possible to translate Petri nets to HDL (Hardware Description Language), and vice versa, making it possible to integrate Petri nets tools into existing design environments. Two main approaches to digital systems design based on Petri nets are direct mapping [3] and logic synthesis [4]. Logic synthesis methods often suffer from the state explosion problem because most modern systems are typically modeled as concurrent systems. Direct mapping methods guarantee an implementation by construction. The size of the obtained circuits is linear on the size of the specification. This paper focuses on some of opportunities of Petri nets utilization in digital systems synthesis based on direct mapping of the behavioral model in FPGA circuits. A proposed CAD tool allows digital system specification, modeling and implementation using ordinary Petri nets. The synthesizable AHDL code is generated from a Petri net model. Proposed method makes possible the structured and flexible FPGA implementation of digital systems. II. DIRECT MAPING OF A PETRI NET MODEL In logic synthesis approach boolean equations for the output signals of the circuit are derived using minimization methods. This approach suffers from excessive computation complexity and memory requirements. The circuit optimization often involves analysis and recalculation of the whole state space. Thus it cannot be applied to large specifications. There is no transparent correspondence between the elements of the original specification, the intermediate representation of the state space and the components of the resultant circuit, which complicates the checking of circuit functionality. The main idea of the direct mapping approach is that a Petri net model of a system is converted into a circuit netlist in such a way that the graph nodes correspond to the circuit elements and graph arcs correspond to the interconnects (Figure 2). The direct mapping method has a linear algorithmic complexity, is not affected by state explosion, so large digital systems can be constructed at low cost. Direct mapping facilities checking of the functional correctness of the implementation because of the transparent correspondence between the elements of the initial HDL Implementation from Petri Nets Description Viorica SUDACEVSCHI, Victor ABABII, Emilian GUTULEAC, Valentin NEGURA Technical University of Moldova str.Stefan cel Mare, 168, MD-2012, Chisinau svm@mail.utm.md; avv@mail.utm.md; egutuleac@mail.utm.md; vnegura@yahoo.fr