Trim Time Reduction in Analog/RF ICs Based on Inter-Trim Correlation V. A. Niranjan * , D. Neethirajan * , C. Xanthopoulos † , E. De La Rosa ‡ , C. Alleyne ‡ , S. Mier ‡ and Y. Makris * * The University of Texas at Dallas, 800 W. Campbell Rd., Richardson, TX, 75080, USA † Advantest America, 12301 Riata Trace Pkwy, Austin, TX 78727, USA ‡ Qualcomm Technologies Inc., 5775 Morehouse Dr., San Diego, CA 92121, USA Abstract—Post-fabrication performance calibration, a.k.a. trimming, is an essential part of analog/RF IC manufactur- ing and testing. Its objective is to counteract the impact of process variations by individually fine-tuning the performance parameters of every fabricated chip so that they meet the design specifications and, thereby, to ensure both high yield and high performance. The prevalent trimming process currently employed in industry involves a search algorithm which consists of repeated digital trim-code selection and measurement in order to optimize the trimmed performance. With hundreds of trims commonly performed on contemporary analog/RF chips, this process becomes overly expensive. In this work, we discuss a machine learning-based approach that ameliorates this problem by leveraging inter-trim correlation. Specifically, our method relies on effectively trained regression models which use the measurements obtained through an intelligently selected and conventionally performed subset of trims, in order to accurately predict the optimal trim codes for the omitted trims. Thereby, as corroborated using data from an actual analog/RF IC currently in production, trim time can be drastically reduced without significantly affecting the accuracy of the selected trim codes. I. I NTRODUCTION The continuous scaling of minimum feature sizes in con- temporary semiconductor manufacturing technologies, which seeks to enable more compact yet more powerful integrated circuits (ICs), has introduced increasingly profound process variation and, by extension, new challenges in the IC design, fabrication and test process. Analog/RF ICs, in particular, have been faced with the challenge of a wider and less controlled distribution of fabricated chip performances due to process variation which, in turn, increases the likelihood of chip performances falling outside their design specification range and resulting in excessive yield loss. As a countermeasure, analog/RF designers have traditionally resorted to conserva- tive margins in order to mitigate the risk, thereby leaving performance on the table. Recently, however, in an effort to achieve high performance through aggressive design while, at the same time, ensuring high yield despite the increased process variation of the latest technology nodes, the concept of post-fabrication performance calibration, or trimming, has been extensively explored [1]–[15]. Trimming methods rely on “tuning knobs,” i.e., circuitry which can be introduced in the design and individually tuned for each fabricated chip after manufacturing, in order to counteract the impact of process variation and bring the per- formances of the chip not only within the design specifications but also as close to their optimal value as possible. Once the appropriate setting for each such tuning knob is decided, it is saved on-chip, usually as a digital code stored in non-volatile or one-time programmable memory. This trimming process is typically performed during manufacturing testing and results in each chip having its own set of trim codes that optimize its performances. In this way, high yield and high performance can be simultaneously achieved. The actual trimming process, however, is a rather challeng- ing and time-consuming. Indeed, the relation between knob positions (i.e., trim codes), process variation and analog/RF IC performances is quite complex. Therefore, industrially deployed and practiced solutions involve worst-case exhaustive algorithms which carry out a directed (usually linear or binary) search in the space of possible trim codes, measuring the target performance for each selected trim code and terminating the search when a target criterion (i.e., performance value) has been reached or when there are no more code options to try. Considering the realities of analog/RF IC testing, which involve expensive instrumentation and lengthy setup and settle times, the duration and cost of such an iterative trim code search process becomes quickly quite onerous. Solutions which can reduce the burden of trim code selection without significantly impacting the quality of the chosen trim codes are, therefore, highly desired. To this end, a variety of approaches have sought to leverage the power of statistical and machine learning methods, along with the correlation amongst continuous measurements in analog/RF ICs, in order to accelerate the process of post- production performance trimming. Specifically, based on the general concepts of alternate test [16] and machine learning- based test [17], numerous statistical trimming methods have been proposed in the literature, using simple measurements from either intrusive or non-intrusive on-chip sensors. Broadly, these methods can be divided into iterative test-&-tune [8], [11], [14] and one-shot [1], [9], [13], [18] approaches. Iterative test-&-tune solutions typically perform a directed search, each time selecting a new trim code and repeating the low-cost mea- surements through which they predict (using trained statistical models) the performances that are being trimmed, ultimately seeking to optimize a target criterion in the space of device performances. One-shot solutions, on the other hand, share the same objective yet use only one set of low-cost measurements for a single trim code in order to build statistical models which enable prediction of the final trim code for a device. Along a different direction to trim cost reduction, the method in [19] uses a lookup table to estimate the trim code, followed by a linear search in the vicinity of the estimated trim code to arrive at the optimal trim code. In [20], the trim 978-1-6654-1949-9/21/$31.00 ©2021 IEEE  2021 IEEE 39th VLSI Test Symposium (VTS) | 978-1-6654-1949-9/20/$31.00 ©2021 IEEE | DOI: 10.1109/VTS50974.2021.9441034 Authorized licensed use limited to: Univ of Texas at Dallas. Downloaded on August 22,2021 at 23:44:32 UTC from IEEE Xplore. Restrictions apply.