Chu-Hsuan Sha Chin C. Lee Electrical Engineering and Computer Science, Materials and Manufacturing Technology, University of California – Irvine, Irvine, CA 92697-2660 40 lm Silver Flip-Chip Interconnect Technology With Solid-State Bonding Formation of pure silver (Ag) flip-chip interconnect of silicon (Si) chips on copper (Cu) substrates is reported. Arrays of Ag columns, each 36 lm in height and 40 lm in diame- ter, are fabricated on 2-in. Si wafers which are first coated with chromium (Cr)/gold (Au) dual layers. The Si wafers are diced into 6 mm  6 mm chips, each having 50  50 Ag columns. The Si chip with Ag columns is directly bonded to Cu substrate at 260  C in 80 mTorr vacuum to inhibit oxidation. The static bonding pressure is as low as 680 psi (4.69 MPa), corresponding to a load of 0.021 oz (0.60 g) per column. During bonding, the Ag columns deform and conform to the Cu substrate. They are well bonded to the Cu. No molten phase is involved in the bonding process. The joints consist of pure Ag only. The ductile Ag joints are able to accommodate the thermal expansion mismatch between Si and Cu. It is well known that in nearly all soldering processes used in electronic indus- tries, intermetallic compound (IMC) formation is essential to make a solder joint. In the pure Ag interconnect, no IMCs exist. Thus, reliability issues associated with IMCs are eliminated. Compared to tin-based lead-free solders, pure Ag joints have superior electri- cal and thermal properties. [DOI: 10.1115/1.4004660] Keywords: silver joints, flip-chip interconnect, solid-state bonding, electronic packaging, Si chips, Cu substrates Introduction At present, nearly all large-scale integrated circuit (IC) chips are packaged with flip-chip technology. This means that the chip is flipped over and the active (front) side is connected to the pack- age using a large number of tiny solder joints, which provide me- chanical support, electrical connection, and heat conduction. For chip-to-package level interconnects, a challenge is the severe mis- match in coefficient of thermal expansion (CTE) between chips and package substrates. Silicon (Si) has CTE of 2.8  10 6 /  C and most III-V compound semiconductors have CTE ranging from 4  10 6 /  C to 7  10 6 /  C. These CTE values are much smaller than that of organic substrates, ranging from 12  10 6 /  C to 18  10 6 /  C[1]. The interconnect material thus needs to be compliant to deal with the CTE mismatch. At present, nearly all flip-chip interconnects in electronic industries are made of lead- free solders such as Sn3.5Ag, Sn0.7Cu and Sn3.8Ag0.7Cu. Soft solders are chosen due to high ductility, low yield strength, rela- tively low melting temperature, and reasonably good electrical and thermal conductivities [2,3]. In the never ending scaling down trend, more and more transis- tors are placed on the same Si chip size. This results in larger pin- out numbers and smaller solder joints. According to International Technology Roadmap for Semiconductors (ITRS), by 2018, the pitch in flip-chip interconnects will become smaller than 70 lm for high performance applications [4]. Two problems occur. The first is increase in shear strain. The aspect ratio of flip-chip joints is constrained to 0.7 because it goes through molten phase in the reflow process. Therefore, smaller joints become shorter as well, resulting in larger shear strain arising from CTE mismatch between Si chips and package substrates. The second is increase in stress in the joints. Since intermetallic compound (IMC) thick- ness in the joint does not scale down with joint size, ratio of IMC thickness to joint height increases. This further enlarges the shear stress because the IMC does not deform as the soft solder does to accommodate CTE mismatch. Our group therefore turned to silver (Ag) flip-chip technology using solid-state bonding. We have successfully demonstrated 250 lm Ag flip-chip technology by solid-state bonding [5]. In the pro- cess, Ag interconnect joints are made between Si chips and Cu substrates at 250  C without using any solder or flux. Cu is chosen because Cu electrodes have been extensively used to mount on Si chips in electronic packages. Cu has a large CTE mismatch with Si, 17  10 6 /  C versus 2.7  10 6 /  C, making bonding of Si to Cu a great challenge. Ag is chosen as the bonding material because it has the highest electrical conductivity (63  10 6 /m  X) and highest thermal conductivity (429 W/m  K) among all metals. There is no IMCs involved. This is in contrast to nearly all solder- ing processes used in electronic industries, where IMC formation is essential to achieve bonding between solder and underbump metallurgy (UBM). The interface between IMC and solder is shown to be the weak interface that tends to break first during thermal cycling and drop tests [6–8]. In this research, we have shrunk the diameter of Ag joints to 40 lm. The Ag interconnect pitch is 100 lm. This is a break- through in the path to the scale down roadmap. In what follows, we first report the design and procedure. Experimental results are then presented and discussed. A short summary is given at last. Experimental Design and Procedure To fabricate Ag columns by electroplating process, 2-in. Si wafers are first deposited with 30 nm of chromium (Cr) and 100 nm of gold (Au) layers by e-beam evaporation in one high vac- uum cycle (3  10 6 Torr). The Cr/Au dual layer is used as seed layer for electroplating as well as the adhesive layer between Ag and Si. Cavities are produced in thick negative photoresist using lithographic process [5]. The photoresist is epoxy with high aspect ratio imaging capability and can be coated up to 120 lm in a sin- gle spinning step. After the photolithographic process, 45 lm Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received January 27, 2011; final manuscript received June 13, 2011; published online September 30, 2011. Assoc. Editor: Guo-Quan Lu. Journal of Electronic Packaging SEPTEMBER 2011, Vol. 133 / 031012-1 Copyright V C 2011 by ASME Downloaded 24 Jan 2012 to 134.134.137.73. Redistribution subject to ASME license or copyright; see http://www.asme.org/terms/Terms_Use.cfm