Page 1 01/12/99 Studying the three-slot asynchronous communication mechanism F. Xia * Department of Computing Science, University of Newcastle upon Tyne I.G. Clark Department of Electronic Engineering, King’s College London Indexing terms: asynchronous data communications, concurrent systems. 1 Abstract The 3-slot asynchronous communication mechanism (ACM) has existed for a long time, but has always been regarded as an inferior solution, especially to the 4-slot ACM, primarily because of questions about its behaviour when individual control variable statements are regarded as non-atomic. With the publication of ACM solutions using mutex elements to deal with metastability, however, any statement protected by a mutex can be regarded as atomic. In such ACM designs it may turn out to be advantageous to use a 3-slot algorithm instead of a 4-slot one with potentially significant savings in silicon. Here the 3- slot method is studied in detail, using a particular algorithm as an example, with certain atomic assumptions consistent with mutex protection of statements. The results confirm promising potential for 3- slot ACMs. 2 Introduction Data communication between processes running in different processors has been extensively studied, especially in distributed and real-time systems. The minimal form of this problem concerns the passing of data between two distributed single-thread processes. One provides the data, which is used by the other. This is schematically shown in Figure 1. process 1 process 2 data Figure 1 Passing data between two processes. In distributed systems, processors may not always share a common clock. When the two processes in Figure 1 are not synchronised, some kind of intermediate data repository, usually in the form of shared memory, is often needed between them to facilitate the data passage. This is schematically shown in Figure 2. process 1 process 2 data repository (shared memory) Figure 2 Passing data via shared memory. An asynchronous data communication mechanism (ACM) is a scheme which manages the transfer of data between two processes not necessarily synchronised for the purpose of data transfer. It is assumed that the data being passed consists of a stream of individual items of a given type. It is also assumed that the processes in question are single thread cycles, one providing an item of data during each cycle, the other making use of an item of data during each cycle. The provider of data is known as the “writer” of the ACM and the user of data is known as the “reader” of the ACM. writer data in shared memory control variables reader Figure 3 ACM using shared memory and control variables. Such techniques as the multiple “slot” (or “track”) mechanisms described in [1], [2] and [3] realise regular and atomic registers in the data path between asynchronous concurrent processes by employing “safe” bit registers to convey the values of bit-size control variables. They avoid conflicts on data memory * Contact: fei.xia@ncl.ac.uk