134 IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 4, APRIL 1998 Back-Gate Bias Enhanced Band-to-Band Tunneling Leakage in Scaled MOSFET’s Ming-Jer Chen, Member, IEEE, Huan-Tsung Huang, Chin-Shan Hou, Member, IEEE, and Kuo-Nan Yang Abstract— The drain leakage current in MOSFET’s in the present standard process is separated into three distinct com- ponents: the subthreshold conduction, the surface band-to-band tunneling (BTBT), and the bulk BTBT. Each of the three shows different dependencies on back-gate bias. As a result, the bulk BTBT, increasing exponentially with increasing the magnitude of back-gate reverse bias, promptly dominates the drain leakage. Additional experiment highlights the effect of the increased bulk dopant concentrations as in next-generation scaled MOSFET’s on the bulk BTBT. This sets the bulk BTBT a significant constraint to the low-voltage, low-power, high-density CMOS integrated circuits employing the back-gate reverse bias. In the work, the measured drain leakage of interest is successfully reproduced by two-dimensional (2-D) device simulation. I. INTRODUCTION T HE leakage in the drain is a big problem for scaling the MOSFET’s toward the deep submicrometer regime. The reasons are that 1) the subthreshold conduction increases exponentially due to threshold voltage reduction [1], [2]; 2) the surface band-to-band tunneling (BTBT) or gate-induced drain leakage (GIDL), increases exponentially due to re- duced gate oxide thickness [3]–[5]; and 3) the bulk BTBT increases exponentially due to increased high doping bulk or pocket concentrations [1], [2]. On the other hand, in the CMOS integrated circuits such as DRAM’s, the back-gate reverse bias or substrate bias has been widely utilized with the following advantages created: suppressing subthreshold leakage, lowering parasitic junction capacitances, increasing immunity against latch-up or parasitic bipolar, etc. Without considering the GIDL and the back-gate bias, the other two leakage components for next-generation scaled MOSFET’s have been projected by Mead [1], pointing to the dominance by subthreshold leakage in the scaling direction down to 0.01- m feature size. In this letter, we demonstrate experimentally that the back- gate reverse bias can significantly enhance the bulk BTBT to the level over the GIDL and the subthreshold conduction, and this situation is more serious in the scaling direction. Manuscript received September 29, 1997; revised October 20, 1997. This work was supported by the National Science Council under Contract NSC 86-2215-E-009-029. M.-J. Chen, H.-T. Huang, and K.-N. Yang are with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. C.-S. Hou is with the Logic Technology R&D Department, Taiwan Semi- conductor Manufacturing Company, Hsinchu 300, Taiwan, R.O.C. Publisher Item Identifier S 0741-3106(98)02628-7. Fig. 1. The schematic cross section of the MOSFET structures under study. The current labeled is the subthreshold conduction, the is the surface BTBT in the gate-to-drain overlap region, and the is the bulk BTBT through the high doping anti-punchthrough region as well as the extra Boron implant region marked by “ ”. II. SEPARATION AND ANALYSIS The n-channel LDD MOSFET’s under test were fabricated in the present standard CMOS process. In this process, Boron ( cm , 120 KeV) and then Boron ( cm , 90 KeV) were implanted to control the punchthrough. The gate width to length ratio was 20 m 0.35 m and the gate oxide thickness was 70 ˚ A. Phosphorus ( cm , 30 KeV) and then Arsenic ( cm , 45 KeV) were implanted to form the low-doped source/drain and Arsenic ( cm , 40 KeV) was implanted to form the highly- doped n source/drain. The simulated doping profile using SUPREM-IV showed that 1) the peak dopant concentration is cm in the gate-to-drain overlap region and 2) the anti-punchthrough implant region, having the peak dopant concentrations of cm , is formed at the bottom junction of the n region. The cross section of the structures under study is schematically shown in Fig. 1. The measured drain current versus gate voltage with back- gate reverse bias as a parameter is shown in Fig. 2 for drain voltage fixed at 3 V and source being grounded. This figure reveals that the drain current for reverse back-gate bias can be separated into two distinct components: one exponentially follows the gate voltage, which is a measure of subthreshold conduction, and another is not affected by gate voltage. The latter component quite matches the measured bulk (p-well) current (not shown here). Thus, the subthreshold component flows from drain to source while the bulk component from 0741–3106/98$10.00  1998 IEEE