Experimental demonstration and analysis of high performance and low 1/f noise Tri-gate MOSFETs by optimizing device structure Weitao Cheng a, * , Akinobu Teramoto a , Tadahiro Ohmi a,b a New Industry Creation Hatchery Center, Tohoku University, Aza-Aoba 6-6-10, Aramaki, Aoba-ku, Sendai 980-8579, Japan b World Premier International Research Center, Tohoku University, Aza-Aoba 6-6-10, Aramaki, Aoba-ku, Sendai 980-8579, Japan article info Article history: Received 3 March 2009 Received in revised form 6 March 2009 Accepted 6 March 2009 Available online 16 March 2009 Keywords: Multi-gate MOSFETs Accumulation-mode 1/f Noise abstract In this paper, we experimentally investigate the performance of multi-gate MOSFETs (MUGFETs) using the advanced radical gate oxide and the accumulation-mode (AM) FD-SOI MOSFETs. Firstly, we experi- mentally demonstrate that the drain current in AM multi-gate MOSFET is improved about 1.3 times com- pared with conventional inversion-mode (IM) MOSFETs with the same gate oxide. Secondly, we indicate that 1/f noise levels in AM MUGFETs are obviously suppressed compared with the conventional IM MUG- FETs. The advantages resulted from the AM device structure for MUGFETs are demonstrated in this experiment. Ó 2009 Elsevier B.V. All rights reserved. 1. Introduction The improvement of the MOS transistor performance and reduction of noise are very important for realizing the high perfor- mance CMOS RF and analog circuits [1]. It has been reported that the current drivability of p-MOSFET on Si(1 1 0) surface is much larger than that on Si(1 0 0) surface [2,3]. Multi-gate MOSFETs (MUGFET) such as the Tri-gate FETs consist of various Si surfaces with different crystal orientations, including Si(1 1 0) and (1 1 0) surfaces, are promising device candidates for the 45 nm node and beyond because of their superior short-channel-effect controllabil- ity. However, it is very important to improve the Tri-gate MOSFETs performance and suppress 1/f noise to turn it into practical use. As the gate insulator thickness is continuously scaled down, it has been reported that the polysilicon gate electrode slightly depletes even its doping concentration is high enough over 10 20 cm À3 . At the same time, it has been reported that the inversion layer capac- itance degrades due to inversion layer quantization effect. The loss of C gc becomes much more significant as the gate insulator thick- ness is scaled down and results in the increase of degradation of the current drivability [4–6]. On the other hand, 1/f noise levels in- crease with scaling down the device size and thinning the gate insulators. In this paper, we demonstrate that Tri-gate MOSFETs perfor- mance is obviously improved and 1/f noise is effectively sup- pressed introducing accumulation-mode (AM) device structure. Finally, we analyzed the device structure and reveal the mecha- nisms for the advantages. 2. Experimental n- and p-MOSFETs on SOI-Si(1 1 0) surface are employed for this experiment. The SOI layer impurity concentration (N sub ) is adjusted for both n- and p-type about 1 Â 10 17 cm À3 by ion implantation be- fore MESA isolation. The thickness of SOI layer (T SOI ) is adjusted to 180 nm. The surface micro-roughness of topside on Si(1 1 0) and sidewalls on Si(1 1 0), (1 1 0) surfaces is suppressed by a radical oxi- dation and then maintained by using 5-step room temperature cleaning [7,8] to avoid the increasing the 1/f noise caused by the surface roughness [9]. The gate oxides are formed by the micro- wave-exited high-density plasma oxidation (radical oxidation) at 400 °C [8]. For AM MOSFETs, P + and B + ions (5.0 Â 10 15 cm À2 ) are implanted to gate poly-Si layer (150 nm) and As + and BF 2 + (1 Â 10 15 cm À2 ) ions are implanted to Source/Drain region for n- and p-MOSFET, respectively. Based on the calculation, the gate poly-Si layer impurity concentration is over 10 20 cm À3 in this experiment. The schematic of these Tri-gate MOSFETs is shown in Fig. 1 with topside on Si(1 1 0) and sidewall on (a) Si(1 1 0) for n-MOSFETs and (b) Si(1 1 0) for p-MOSFETs. These devices are pat- terned using electron beam lithography setup CABLE-9520. At the 1/f noise measurement, the drain current noise measurements were carried out using a Vector Signal Analyzer (AGILENT 89410A) connected to a low noise preamplifier (Princeton Applied Research 5184) with contacts directly taken on wafer. Each step of device fabrication and measurement was carried out in the 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.03.062 * Corresponding author. Tel.: +81 22 795 3977; fax: +81 22 795 3986. E-mail address: cheng@fff.niche.tohoku.ac.jp (W. Cheng). Microelectronic Engineering 86 (2009) 1786–1788 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee