Communicating Process Architectures – 2002 James Pascoe, Peter Welch, Roger Loader and Vaidy Sunderam (Eds.) IOS Press, 2002 1 Semantics of prialt in Handel-C TM Andrew BUTTERFIELD 1 and Jim WOODCOCK 2 1 Dublin University 2 University of Kent at Canterbury Andrew.Butterfield@cs.tcd.ie Abstract. This paper discusses the semantics of the prialt construct in Handel- C[1]. The language is essentially a static subset of C, augmented with a parallel construct and channel communication, as found in CSP. All assignments and chan- nel communication events take one clock cycle, with all updates synchronised with the clock edge marking the cycle end. The behaviour of prialt in Handel-C is similar in concept to that of occam [2, 3], and to the p-priority concept of Adrian Lawrence CSPP [4]. However, we have to contend with both input and output guards in Handel-C, unlike the situation in occam, although prialts with conflicting pri- ority requirements are not legal in Handel-C. This makes our problem simpler than the more general case including such conflicts considered in [4]. We start with an informal discussion of the issues that arise when considering the semantics of Handel- C’s prialt construct. We define a resolution function (R) that determines which requests in a collection of prialts become active. We describe a few properties that we expect to hold for resolution, and discuss the issue of compositionality. 1 Introduction This paper discusses the semantics of the prialt construct in Handel-C[1], a language originally developed by the Hardware Compilation Group at Oxford University Computing Laboratory. It is a hybrid of CSP [5] and C, designed to target hardware implementations, specifically field-programmable gate arrays (FPGAs) [6, 7, 8, 9]. The language is essentially a static subset of C, augmented with a parallel construct and channel communication, as found in CSP. The type system has been modified to refer explicitly to the number of bits required to implement any given type. The language targets largely synchronous hardware with a multiple clock domains. All assignments and channel communication events take one clock cycle, with all updates synchronised with the clock edge marking the cycle end. All expression and conditional evaluations are deemed to be instantaneous, effectively being completed before the current clock-cycle ends. 1.1 Notation In Handel-C, a typical program fragment showing two prialts in parallel might appear as: par { prialt { a!11 : P1 ; break ; b?x : P2 ; break ; } ; prialt { b!22 : P3 ; break ; c?y : P4 ; break ; } }