1.2 GS/s Hadamard Transform Front-End For Compressive Sensing in 65nm CMOS Osama U. Khan, David D. Wentzloff University of Michigan, Ann Arbor, MI, USA. Abstract — In this paper we present a digitally assisted front-end that performs analog computation of the Walsh Hadamard Transform (WHT) for GHz ADCs using compressive sensing to reduce power. The circuit consumes 11.2mW of power while sampling at 1.2GHz. The achieved compression rate assuming an ideal ADC is 59.4% with a mean square error of 0.3%. Comparison with the Nyquist ADC shows that using the sub-Nyquist ADC with the proposed WHT front-end reduces power by a factor of about 6x. Index Terms — Compressed sensing, sub-Nyquist ADC, Walsh Hadamard Transform. I. INTRODUCTION Compressive Sensing (CS) theory states that given a signal is sparse in one domain (e.g. a pulse in the time domain); it can be sampled randomly in an orthogonal domain (e.g. the frequency domain) at a rate less than suggested by the Nyquist sampling theorem. The sparse signal can then be recovered with high probability from these compressed samples, but with an error proportional to the compression rate, by using a recovery algorithm (e.g. L1 minimization) [1]-[2]. Our signal of interest is a baseband ultra-wide-band (UWB) pulse with a width on the order of a nanosecond which is sparse in the time domain. The Nyquist sampling rate for a UWB pulse requires ADC sampling at a frequency greater than 500MHz, which usually results in prohibitively large power consumption in the ADC. This power can be a significant fraction of the total power consumption of the entire system. In [3] [4] [5] the power consumption for a 6-bit ADC with GHz sampling rate is greater than 150mW, which might be excessive for certain wireless applications. Sampling the UWB signal below the Nyquist rate, while maintaining a certain performance, may lead to a low power alternative solution. There exist many potential orthogonal domains suitable for compressive sensing. In this paper, we implement the Walsh Hadamard Transform (WHT) as a measurement matrix to be used in CS. The reason for choosing the WHT is Walsh codes are a sequence of ±1’s that multiply the time signal and the inversion can be easily implemented in hardware. Fig. 1 shows the block diagram of a system exploiting CS and the discrete-time WHT front-end. In this work an Analog WHT is computed on the incoming sparse signal, the output of which is sub-Nyquist sampled by randomly choosing K samples out of N Nyquist samples. These compressed samples are then post processed by a recovery algorithm [6] which reconstructs the original sparse signal. Simulation was performed to compare the proposed system with a Nyquist ADC. An ideal WHT is computed on the sparse signal and the resulting Hadamard coefficients are quantized with finite resolution. It is found that for K≥N/3 random samples, the Mean Square Error (MSE) between the original and the recovered signal is limited by the finite ADC resolution rather than the number of sparse samples, K. Further, for the same Mean Square Quantization Error (MSQE) a sub-Nyquist ADC quantizing a sparse time signal in the Hadamard domain can save one bit of resolution. Combining these two factors, a sub-Nyquist ADC with the same Figure of Merit (FoM) can be made lower power by a factor of about 6. Fig. 1 Block diagram II. CIRCUIT DESCRIPTION The circuit computes a 64-point WHT. The system comprises custom analog and synthesized digital logic. The function of the latter is to provide the necessary control (e.g. Walsh codes) to the analog blocks. The Hadamard coefficients are the inner products of the input signal with the Walsh codes as shown in matrix form in Fig. 2. To compute the WHT the incoming signal is correlated with the Walsh codes using a GHz sampling rate and discrete-time integration. The speed requirement of the sampling and integration are met by splitting the correlation operation into three identical time-interleaved channels as shown in Fig. 1. A 6-bit LFSR generates a pseudo random number which is used by the on-chip Analog WHT Recovery Algorithm K<<N CS LFSR Controller 4 This Work Digital APR Custom Analog Controller Differential S/H ∫ Walsh Generator (WG) ∑ Channel 1 LFSR Amplifier Summing Amplifier Channel 2 3 Sub-Nyquist ADC 978-1-4673-2932-3/13/$31.00  2013 IEEE RWS 2013 181