2017 Paciﬁc Southwest Section Meeting: Tempe, Arizona Apr 20 Paper ID #20694 Empirical Learning of Digital Systems Testing and Testable Design Using Industry-Veriﬁed Electronics Design Automation Tools in Classroom Dr. Reza Raeisi, California State University, Fresno DR REZA RAEISI a Professor of Electrical and Computer Engineering Department at California State University, Fresno. He is also Chair of he ECE department. His research interests include integrated circuits, embedded systems, and VLSI-CAD technology. He serves as Paciﬁc Southwest regional director of American Society of Engineering Education. He is an entrepreneur with over 20 years of domestic an international experience and professional skills in both industry and academia. Dr. Raeisi may be reached at rraeisi@csufresno.edu Mr. Vidya sagar reddy Gopala P.E., California State University, Fresno Vidya sagar reddy Gopala received the B.E. in Electronics and Communication from Visvesvaraya Tech- nological University of India (2015). He is currently perusing M.S. in Computer Engineering at California State University,Fresno. He works as teaching and Graduate Assistant in the Department of Electrical and Computer Engineering at California State University, Fresno. His research interests include NOC, VLSI design, system testing, testable design and veriﬁcation. c American Society for Engineering Education, 2017