International Research Journal of Engineering and Technology ( I RJET) e-ISSN: 2395 -0056 Volume: 02 Issue: 03 | June-2015 www.irjet.net p-ISSN: 2395-0072 © 2015, IRJET.NET- All Rights Reserved Page 880 Design of High Speed 64x64 Bit Fault Tolerant Reversible Vedic Multiplier Akansha Sahu 1 ,Anil Kumar Sahu 2 1 ME Student ,Electronic & Telecommunication Engg , SSTC, Chhattisgarh, India 2 Assistant Professor, Electronic & Telecommunication Engg, SSTC, Chhattisgarh, India ---------------------------------------------------------------------***--------------------------------------------------------------------- Abstract - Multiplier is the most widely used arithmetic unit, having great importance in the digital world. For example- Digital Signal Pr ocessing, Processor and Quantum Computing etc. The Multiplier is the slowest and having a complex structure. In this paper a 64x64 bit high speed and fault tolerant multiplier architecture is proposed .The speed of the multiplier is enhanced with the help “Urdhva Tiryakbhayam” aphorisms from the ancient Vedic Indian Mathematics. Further the architecture of the multiplier is implemented using the Fault Tolerant Reversible Gates which exhibits a fault tolerant property by preserving the parity. Hence the parity checking method is used to find out the error and correction. Finally the Partial Product of the multiplier is added with the help of fault tolerant Carry look ahead adder. The coding is written in Verilog .While synthesis and simulation is performed using Xilinx 14.7i. Key Words: Delay, Fault Tolerant Reversible gate, Vedic Method , Carry look ahead Adder. 1. INTRODUCTION As the technology is scaling down from micro scale to nano scale . At such scale a new field is evolved is called quantum computing. Quantum computation based on the principle of reversible operation, means the information is conversed and performs certain task in nanosecond. [1]These are the main motivation to develop a high speed multiplier using reversible logic gates. In order to implement a high speed multiplier an Vedic algorithm is applied .Because it perform simple operation and yield result quickly. The multiplication process involves two step generation of partial product and addition of partial product , these two steps are concurrently perform by the Urdhva Tiryakbhyam algorithm of Vedic Mathematics .[5] This paper proposes the implementation of fault tolerant reversible Vedic multiplier , with the aim to develop a high speed multiplier with Vedic method and the architecture of multiplier is implemented with fault tolerant reversible gate in order to improves the reliability, reduces area. The paper is describe under the following sections : Section 2 explain Reversible logic Gates, Section 3 Urdhav Tiryakbhyam aphorism, Section 4 Fault Tolerant Carry Look Ahead Adder Section 5 Proposed 64x64 bit Fault Tolerant Reversible Vedic Multiplier Architecture Section 6 shows the Result and Comparison and Section 7 shows the Conclusion. 2. REVERSI BLE LOGI C GATES Reversible logic perform reversible computation means that the input can be recovered back from the output and the output can also be obtained from the input . Hence the reversible logic circuit are also called as the Information loss-less logic. Reversible logic is classified into types they are Basic Reversible gate and Fault Tolerant Reversible Gates. Reversible gate are those gates having the same number of the input lines and the output line. While Fault tolerant Reversible gate are also known as the parity preserving reversible gate which performs reversible computation as well as the preserve the parity at the input side as well as at the output side.[12] Some of the Fault Tolerant Reversible Gate are shown in the below: 2.1 Double Feynman Gate The double Feynman gate is a 3*3 gate are shown in the fig1. The input vector is I(A,B,C) and output vector is O( P,Q,R). The input parity is same as the output parity .Quantum Cost of F2G is equal to 2. A B C P=A Q=AB Double Feynman Gat e R=AC Fig- 1 : Feynman Gate