Design of Injection-Locked Frequency Divider in 65 nm CMOS Technology for mm-W applications Davide Brandano and José Luis González, Member, IEEE Departament d'Enginyeria Electrònica Universitat Politècnica de Catalunya (UPC) Barcelona, Spain Abstract—In this paper, an Injection Locking Frequency Divider (ILFD) in 65 nm RF CMOS Technology for applications in millimeter-wave (mm-W) band is presented. The proposed circuit achieves 12.69% of locking range without any tuning mechanism and it can cover the entire mm-W band in presence of Process, Voltage and Temperature (PVT) variations by changing the Injection Locking Oscillator (ILO) voltage control. A design methodology flow is proposed for ILFD design and an overview regarding CMOS capabilities and opportunities for mm-W transceiver implementation is also exposed. Keywords: mm-W; prescaler; frequency divider; injection locking; locking range; I. INTRODUCTION Increasing memory capacity in mobile devices, together with the transition to wireless connections for consumer electronics and PC products, is driving the need for wireless equipment with data rates of up to 10 Gbits/sec. The worldwide 9 GHz mm-W unlicensed band (57 to 66 GHz) provides the opportunity for multi-gigabit wireless communication and it is a real opportunity for developing next generation Wireless High-Definition Multimedia Interfaces (WHDMIs). The allocated bandwidth at 60 GHz varies from country to country as shown in Fig. 1. Mass production requirements coupled with the cost constraints of mobile devices result in a need to identify an alternative to existing, expensive Gallium Arsenide (GaAs) and Indium Phosphide (InP) technologies, currently used widely in mm-W Microwave Monolithic Integrated Circuit (MMIC) fabrication. RF CMOS 65 nm technology currently show very attractive performance for mm-W MMIC design [1]-[2], even if the technology environment is a critical issue in the design of frequency synthesizers operating at mm-W frequencies. Recent developments in mm-W CMOS systems have begun to address the integration of building blocks to form transceivers. In addition to generic challenges such as high- frequency operation and low-noise design, the implementation of transceivers at these frequencies must deal with three critical issues related to the frequency synthesis, that are generation, division and distribution [3]. Millimeter wave frequencies have historically been costly to utilize. Recent advances in semiconductor technology provide an opportunity for this spectrum to become useable for broadband consumer applications within the next 2-3 years. The aim of this work is to design a frequency divider for a PLL of a transceiver operating at mm-W frequencies in 65 nm RF CMOS technology; several issues will be faced, like Process, Voltage and Temperature (PVT) variations and power consumption, in order to select and design a frequency divider with high locking-range. Figure 1. Spectrum available around 60 GHz II. ARCHITECTURES FOR TRANSCEIVERS In this section different transceiver architecture topologies are explored, from the frequency synthesis point of view. A. Heterodyne Transceiver Architecture In heterodyne architecture, the signal band is translated to “much lower” frequencies. The frequency translation is carried by means of a mixer which could be viewed also as a simple analog multiplier. The problems that affect heterodyne architecture are the “image-frequency” and the channel selection. Also, the effect of the half IF in a heterodyne receiver must be considered [4]. The trade off between sensitivity and selectivity in the basic heterodyne architecture often proves quite difficult to optimize with a single conversion stage. To resolve this issue, the concept of heterodyne can be extended to multiple down/up- conversions. The second down-conversion typically comprises both in-phase (I) and quadrature (Q) components of the signal. This technique allows skipping a second intermediate frequency stage. In Fig. 2, the heterodyne receiver architecture with double conversion is shown. Two LO signals at different frequencies are required, obtained, in this case, by frequency multiplication and division from a single VCO: ISBN 978-84-693-7393-4 DCIS 2010 Proceedings 76