International Conference on Magnetics, Machines & Drives (AICERA-2014iCMMD) Implementation of High Performance Dynamic Flash ADC Titu Mary Ignatius, Jobin.K.Antony, Silpa Rose Mary Rajagiri School of Engineering and Technology, Kochi, Kerala, India titu.mathew2011@gmail.com, jobinka@rajagiritech.ac.in, silparosemary@gmail.com Abstract—Dynamic Flash ADC has lot of applications in real time systems and mixed signal systems, where analog signals are converted to digital signals and then processed. In the present work, a new high performance dynamic Flash ADC is designed, which employs fast thermometer encoder and low power open loop comparator. Subsequently, a dynamic Flash ADC using standard cells such as NAND, NOR and INVERTER is also designed and implemented. Various parameters of the new dynamic Flash ADCs are analysed and it is found that these designs are best suited for low power applications. These dynamic Flash ADCs are designed in 180nm technology and post layout simulation is performed using Cadence Spectre tool. Index Terms—dynamic Flash ADC; dynamic thermometer encoder ; Open loop comparator; Cadence Spectre; post-layout; I. I NTRODUCTION In nature all signals are analog and it is difficult to process and analyse analog signals directly. Moreover analog signals are more prone to noise and interference of side band signals. Design and verification of analog circuits are more difficult compared to digital circuits and scaling down of analog circuit deals with several design issues. In almost all practical applications it is required to convert analog signal to digital signals using suitable ADC and which is the key component in modern electronic systems and mixed signal systems. The general block diagram (Fig.1) of an analog to digital converter has an anti-aliasing filter, sample and hold circuit and Flash ADC[6-7]. Anti-aliasing filters are used to prevent aliasing effect. Sample and hold circuits are used for sampling, which convert analog signal to discrete signal. Sampling is done at Nyquist rate, f s =2f m . Flash ADC quantizes and convert discrete signal to digital signal. Fig. 1. Block Diagram of a Practical ADC Many flash ADCs architectures [4-7] are reported in the literature. N-bit Flash ADC, has 2 N resistors in resistor ladder, which produces the reference voltages, and 2 N − 1 compara- tors, which compare the applied input signal with reference voltage and produce either 1 or 0, depending on whether input signal is greater than reference or not. If V in >V ref , then output of comparator is logic 1, else logic 0. The output generated by a set of comparators is thermometer code, where a group of 0s are followed by a group of 1s. The thermometer code is converted to binary code using encoders. The Fig.2 shows a 3-bit Flash ADC, which requires 8 resistors and 7 comparators. Fig. 2. Circuit level representation of Flash ADC There is a wide selection of comparators such as conven- tional comparator, comparator 1[2] and open loop comparator [9] and thermometer encoders such as XOR encoder [3]and Wallace tree encoder [8] in the literature. Most of the systems use conventional comparator[2], which require large number of transistors. Traditional comparators are replaced by low power comparators such as comparator 1[2] and open loop comparator[9]. Open loop comparator[9] is best suited for low power application. In the present work a high performance dynamic Flash ADC is designed and implemented using the fast dynamic thermome- ter encoder and low power open loop comparator. It has been observed that the new dynamic flash ADC is area-efficient, as the number of transistors is reduced by 50%. Also it is best suited for low power applications. Later-on a dynamic standard cell Flash ADC has been designed and implemented. The above mentioned ADC is technology independent, since 978-1-4799-5202-1/14/$31.00 c 2014 IEEE 1