A Simple Power Consumption Model of CMOS Buffers Briving RC Interconnect Lines J.L. Rossello and Jaume Segura Balearic Islands University, Palma de Mallorca 07071, SPAIN {j.rossello,jaume.segura}@uib.es Abstract. We present a simple and accurate model to compute the power dissipated in sub-micron CMOS buffers driving RC interconnect lines. The expression obtained accounts for the main effects in current sub-micron CMOS technologies as carrier velocity saturation effects, input-output coupling capacitor, output load, input slew time, device sizes and interconnect resistance. Results are compared to HSPICE sim- ulations (level 50) and other models for a 0.18μm and a 0.35μm tech- nologies showing significant improvements. 1 Introduction As IC technology fabrication processes scale down, new physical effects must be con- sidered when analyzing and modeling CMOS circuits. Velocity saturation due to high internal electric fields, input-output coupling capacitor effects due to the narrower gate oxide thickness, and on-chip interconnect resistance (that does not scale down with feature size) are some of the effects that must be considered to obtain accurate mod- els. A large fraction of the power dissipated in today VLSI ICs is due to the I/O drivers and busses and the clock distribution network, which are based on inverter gates. Hence, the analytical description of power dissipated in a CMOS inverter is of increasing importance for CMOS ICs power estimation. It is well known that power dissipation in CMOS circuits has a dynamic and a static component. The dynamic dissipation (defined as transient energy) is due to the charge/discharge of the gate output load, and to the short-circuit current due to the supply-ground conducting path created during the transition. Several works have been focussed on modeling the short-circuit power consumption of CMOS buffers. Nose et al. [1] derived a model for submicron CMOS buffers driving a single capacitor. This model does not take into account both the input-output coupling capacitor (IOCC) effects nor the line resistance at the buffer output. Turgis et al. [2] derived an expression for the short-circuit power taking into account the IOCC and neglecting the resistance at the buffer output. Nikolaidis et. al [3], obtained an expression of the short-circuit dissipation for buffers driving long interconnect lines using the α−power law MOSFET model. The analysis was based on the π-model of an RC load and developed for sub- micron devices. This model takes into account the IOCC but neglects the short-circuit current contribution when computing the output waveform. In this work we present an accurate and simple model to compute the power con- sumption of CMOS buffers accounting for the main effects in submicron CMOS tech- nologies as the IOCC and the line interconnect resistance, of increasing importance in current submicron ICs. Closed-form expressions for power estimation are obtained