SUPPORTING INFORMATION FOR ACTIVE MODULATION OF DRUG RELEASE BY IONIC FIELD EFFECT TRANSISTOR FOR AN ULTRA-LOW POWER IMPLANTABLE NANOFLUIDIC SYSTEM Giacomo Bruno, †,§,‡ Giancarlo Canavese, ¥,‡ Xuewu Liu, † Carly Filgueira, † Adriano Sacco, # Danilo Demarchi, § and Alessandro Grattoni †,* † Department of Nanomedicine, Houston Methodist Research Institute, 6670 Bertner Avenue, Houston, TX 77030, USA § Department of Electronics and Telecommunications, Politecnico di Torino, Corso Duca degli Abruzzi 24, Turin 10129, Italy ¥ Department of Applied Sciences and Technology, Politecnico di Torino, Corso Duca degli Abruzzi 24, Turin 10129, Italy # IIT - Italian Institute of Technology, Center for Sustainable Futures @POLITO, Corso Trento 21, Turin 10129, Italy Nanofluidic device fabrication process. The nanofluidic devices were composed of a silicon substrate and a pyrex cap with integrated electrodes. The processing of the silicon substrates started with double side polished p-type 4 inch wafers. To fabricate the nanochannels, a pad oxide layer was deposited followed by a layer of nitride on wafers. Then, standard lithography was applied to generate nanochannel patterns. CF4 reactive ion etching (RIE) was then used to remove nitrides on these channel patterns. Etching time was controlled so that there was a thin layer of silicon dioxide remaining to prevent reactive ions from attacking the silicon underneath. A diluted HF solution was used to clean the oxide in channel patterns. The silicon wafers were put into thermal oxide furnace and a desired amount of oxide was grown. The thickness of oxide defined the height of nanochannels and was measured by using ellipsometry. HF solution was then used to remove all dielectrics on the substrates. A new layer of silicon nitride was deposited for the second major step to define the inlet and outlet microchannel areas. After patterning these on top of nanochannels, RIE was performed. The third major step was creating the back side openings. A new layer of silicon nitride was deposited on the silicon substrates. The exit ports were patterned on back of the wafers by double side alignment. CF4 RIE was used to open the exit port pattern. Then KOH etching was performed (approximately eight hours) to etch through silicon wafers. After removing dielectric materials using HF solution, a 15 nm thick silicon oxide layer was deposited as an insulating layer for easy wire bonding. The real nanochannel height was measured using AFM. 5 selected points were measured for each substrate. The completed microfabricated silicon substrate is shown in Figure S1. Figure S1. Microfabricated nanofluidic silicon substrate with parallel set of slit-nanochannels Pyrex glass fabrication. A sandwich of titanium, gold and titanium was evaporated on four inch pyrex wafers. Then, standard lithography was used to pattern the electrodes. Multi-step wet etching was applied to etch the Ti-Au-Ti sandwich, and the remaining photoresist was then cleaned up. Here, the height of electrodes was 150 nm above the pyrex surface. Then, a lift-off process was performed to match the thickness of electrode with evaporated pyrex glass film. To do so, a photolithograph was performed to cover the electrodes followed by a 150 nm glass film evaporation using CHA. Next, the wafer was sonicated in acetone to remove the photoresist and clean the deposited pyrex on the top of electrodes. After that, a 100 nm thick pyrex film was evaporated to cover electrodes. Then, a CMP step was applied to polish the surface to reach desired roughness. Much effort was used to optimize the CMP process. During CMP process, many parameters such as pressure, speed, time, and pads, needed to be controlled. The surface roughness was finally reduced to 1 to 2 nm. The CMP processing was monitored by AFM. Anodic bonding. Inlet openings were drilled into the pyrex wafers by Bullen Ultrasonics. The anodic bonding of pyrex and silicon wafers were done using Ohio State University facilities. The bonding conditions were 350 °C, 450 V, compressive force 500 N and were maintained for 20 minutes. Finally, the wafers were cleaned and diced. 1 Electronic Supplementary Material (ESI) for Nanoscale. This journal is © The Royal Society of Chemistry 2016