Int. J. Nano Dimens., 10 (4): 368-374, Autumn 2019 ORIGINAL ARTICLE Improved drain current characteristics of tunnel feld efect transistor with heterodielectric stacked structure Vimala Palanichamy*, Netravathi Kulkarni, Arun Samuel Tankamony Sarasam Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, Bangalore, India Received 01 June 2019; revised 17 July 2019; accepted 23 July 2019; available online 30 July 2019 * Corresponding Author Email: ervimala@gmail.com How to cite this article Palanichamy V, Kulkarni N, Tankamony Sarasam AR. Improved drain current characteristics of tunnel feld efect transistor with heterodielectric stacked structure. Int. J. Nano Dimens., 2019; 10 (4): 368-374. Abstract In this paper, we proposed a 2-D analytical model for electrical characteristics such as surface potential, electric feld and drain current of Silicon-on-Insulator Tunnel Field Efect Transistor (SOI TFETs) with a SiO 2 / High-k stacked gate-oxide structure. By using superposition principle with suitable boundary conditions, the Poisson’s equation has been solved to model the channel region potential. Te modeled channel potential is to calculate both vertical and lateral electric feld. 2-D Kane’s model is used to calculate the drain current of TFET and the expression is taken out by analytically integrating the band-to-band tunneling generation rate over the thickness of channel region. Te device is modeled in variation with diferent device parameters like channel length (L CH ), dielectric thickness (t ox ), silicon thickness (t si ) and input voltage (V ds and V gs ). Also, the comparison of SiO 2 and stacked high k dielectric TFET is obtained. It has been found from the presented results that the hetero-dielectric stacked TFET structure provides ON current 10 -6 A/um. However, SiO 2 dielectric structure provides the ON current of 10 -8 A/um. Te proposed model is validated by comparing it with Technology Computer-Aided Design (TCAD) simulation results obtained by using SILVACO ATLAS device simulation sofware. Keywords: Analytical Modeling; High-k Dielectric; Poisson’s Equation; Superposition Principle; Tunnel FET (TFET). Tis work is licensed under the Creative Commons Attribution 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/. INTRODUCTION In this era of modern VLSI industry, power efcient and economical semiconductor devices play a major role in the semiconductor market. To cater this and improve efciency of the device, the dimensions of the Metal oxide semiconductor feld efect transistors (MOSFETs) are being contnuously scaled down in nano meter range [1-4], resultng in accreton of few performance limitatons called as Short Channel Efects (SCE). By using various novel devices like impact-ionizaton MOS devices [5-7], Nano-Electro Mechanical FETs (NMFETs), Suspended Gate MOSFETs, Mult Gate MOSFETs, Silicon on Insulator Field Efect Transistors (SOI FETs), Fin FETs, etc., these efects are overwhelmed. Yet power efciency being the major issue in these novel devices, Since an assuring device structure is modelled to improve power efciency termed as Tunnel Field Efect Transistors (TFETs) [8, 9]. This is a beter replacement for MOSFETs because of its low and steeper sub threshold swing (SS) less than 60 mV/dec (SS for conventonal MOSFETs limited to 60 mV/decade). In order to improve the ON current [10-14] of these devices high-k materials are stacked with SiO 2 in gate dielectric region, by this electrical characteristc of the TFETs are improved. In this paper, a 2-D analytcal soluton of SOI TFETs with a SiO 2 /High-k stacked gate-oxide structure has been presented. A two-dimensional Poisson’s equaton has been solved to derive the analytcal expressions for surface potental and electrical feld. By varying the surface potental, the electric feld is obtained and is used for deriving the drain current by applying Kane’s model [15] for tunnelling. This paper is presented as follows: The device structure of high-k stacked gate oxide TFET is explained in the secton II. The adapton of 2-D