IEEE TRANSACTIONS ON CIRCUITSAND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 7, JULY 2004 1301 An Analytical Charge-Based Compact Delay Model for Submicrometer CMOS Inverters José Luis Rosselló and Jaume Segura Abstract—We develop an accurate analytical expression for the propagation delay of submicrometer CMOS inverters that takes into account the short-circuit current, the input–output coupling capacitance, and the carrier velocity saturation effects, of increasing importance in submicrometer CMOS technologies. The model is based on the th-power-law MOSFET model and com- putes the delay from the charge delivered to the gate. Comparison with HSPICE level 50 simulations and other previously published models for a 0.18- m and a 0.35- m process technologies show significant improvements over previous models. Index Terms—Analytical model, circuit modeling, delay estima- tion, submicrometer MOSFETs. I. INTRODUCTION T IMING analysis is one of the most critical topics in very large-scale integration (VLSI) design. The nonlinear behavior of CMOS gates requires numerical calculations for accurate timing analysis at the expenses of large computation times. Moreover, the impact of design parameters such as fan-in, fan-out, or transistor sizes on the propagation delay are difficult to understand and optimize using numerical procedures. The dynamic behavior of submicrometer CMOS inverters de- pends on several nonlinear effects like the velocity saturation of carriers due to the high electric fields in submicrometer tech- nologies, the short-circuit current appearing when both pMOS and nMOS transistors conduct simultaneously [1], and the ad- ditional effect of the input–output coupling capacitance [2]. Several methods have been proposed to derive the delay of CMOS inverters [2]–[8] as a first step to describe more complex gates [9], [10]. Cocchini et al. [3] obtained a piecewise expression for the propagation delay based on the Berkeley short-channel IGFET model (BSIM) MOSFET model [11]. The model included overshooting effects (due to the input-to-output coupling capacitance) while the short-circuit current was neglected. Jeppson in [2], and Bisdounis et al. in [4], presented a model for the output response of CMOS inverters using a quadratic current-voltage dependence for MOSFET devices which is not longer valid for submicrometer technologies. Daga and Auvergne [5] obtained an empirical expression for Manuscript received May 25, 2003; revised August 31, 2003. This work was supported in part by the Spanish Ministry of Science and Technology, in part by the Regional European Development Funds (FEDER) under EU Project TIC2002-01238, and in part by Intel Laboratories-CRL. This paper was recommended by Associate Editor A. I. Karsilayan. The authors are with the Physics Department, Balearic Islands University, 07071 Palma de Mallorca, Spain (e-mail: j.rossello@uib.es; jaume.segura@ uib.es). Digital Object Identifier 10.1109/TCSI.2004.830692 the propagation delay taking into account both overshooting and short-circuit currents. Hirata et al. [6] derived a propagation delay model with numerical procedures based on the th-power-law MOSFET model [12] considering both short-circuit and overshooting currents. The model provides an accurate description of the propagation delay but the numerical procedures used in their analysis increase the computation time considerably. Bisdounis et al. [7] developed a piecewise solution with seven operation regions for the transient response of a CMOS inverter based on the -power-law MOSFET model [13] including both overshooting and short-circuit currents. Recently, Kabbani et al. obtained, in [8], a transition time model considering a quadratic relationship between the saturation current and the gate–source voltage (assumption only valid for micronic devices) without considering the effect of the input–output coupling capacitance. In [9], Sakurai and Newton obtained a simple expression for the propagation delay of CMOS gates based on their th-power-law MOSFET model neglecting both short-circuit and overshooting currents. In this paper, we propose an analytical model to accurately compute the propagation delay of a CMOS inverter accounting for the main effects of submicrometer technologies like the input–output coupling capacitance, carriers velocity saturation effects and short-circuit currents. The model is based on an accurate physically-based th-power-law MOSFET model [14] and on a previous power dissipation model for CMOS inverters [15]. The model can be applied to compute the propagation delay of CMOS inverters and represents a valuable approach for the evaluation of delay in complex gates as these can be collapsed to a single equivalent inverter for delay evaluation [10]. Comparisons with previously published models and HSPICE simulations using the Philips MOSFET Model 9 (MM9) for 0.18- m and 0.35- m process technologies show significant improvements in terms of accuracy. This paper is organized as follows. In Section II, we describe briefly the switching characteristics of CMOS inverters and introduce the MOSFET device model used in this work. In Section III, we derive an analytical charge-based expression for the switching response of a single pMOS/nMOS transistor charging/discharging a capacitor, that are generalized to CMOS inverters in Section IV by including overshooting and short-cir- cuit effects. Section V presents an analytical model for the output transition time based on the delay model developed. The model proposed is compared to HSPICE simulations and other previously published models for a 0.35- m and a 0.18- m process technology in Section VI. Finally, in Section VII, we conclude the paper. 1057-7122/04$20.00 © 2004 IEEE