International Journal of Recent Technology and Engineering (IJRTE) ISSN: 2277-3878, Volume-8 Issue-3, September 2019 4680 Published By: Blue Eyes Intelligence Engineering & Sciences Publication Retrieval Number C6847098319/2019©BEIESP DOI: 10.35940/ijrte.C6847.098319 Abstract— In this paper, modified-Gate Diffusion Input (M-GDI) based binary counter is designed using symmetric stacking method. The binary counter is designed using 3-bit stacker circuit that groups the one bit together and symmetric method is used to form 6-bit stack. The 6-bit stack is converted to binary count to produce required counters. The M-GDI is used to further reduce the transistor count than the CMOS logic transistor count. Mainly the basic gates are developed using the M-GDI technique and the basic gates are replaced in the 6:3 counters to further improve counter-performance. The proposed 6:3 binary counter has no Exclusive or gate (XOR) gates on the critical path, which leads to faster performance of the circuit. The proposed counter is faster, also consumes less power than the traditional. By using this proposed counter in Wallace multiplier, the delay and power for higher-order multipliers is reduced. This paper proposes a novel symmetric stacking based fast binary counters using the modified gate diffusion input (M-GDI) technique. This paper proposes a novel binary counter. Keywords: Counters, Modified GDI, Stacker circuit, Wallace Tree I. INTRODUCTION Majority of applications require an efficient processor to perform the processing on a large amount of data [1]. Delay, power, and area are the main parameters which determine the performance of any circuit. The performance of the processor is increased by improving the performance of the multiplier block [1]. The multiplication process mainly includes partial product reduction, final carry propagation addition and partial product generation [1]. The power consumption and delay of the multiplier is determined by the partial product reduction. Various counters have already been proposed in the literature for the better performance of the partial products reduction stage [2-5]. Full adder circuits are used in the full adder-based counters to construct the 6:3 counter [2]. The delay increases in the higher-order counters due to the presence of the XOR gates in the full adder circuits and also average power increases due to the presence of more number of transistors in the full adder-based counters. Basic gates are used in the parallel counters to construct the 6:3 counters [3]. It was found that this approach gave less delay and average power over [2]. However, this approach gave more transistor Revised Version Manuscript Received on 30 May, 2018. Pavani Ivaturi, Department of Electronics and Communications, Shri Vishnu Engineering College for Women (Autonomous), Bhimavaram, Andhra Pradesh, India. N. Prasad, Department of Electronics and Communications, Shri Vishnu Engineering College for Women (Autonomous), Bhimavaram, Andhra Pradesh, India. count than [2]. A method to further reduce the delay and average power over [2, 3] has been proposed in [4], where multiplexers are used to construct the 6:3 counters. It was found that this approach gave less transistor count over [2, 3]. The 3- bit stacker circuits and basic gates are used in the symmetric stacking-based counter to construct the 6:3 counter [5]. It was found that this approach gave better performance over [2-4]. Counters should provide less delay and average power. These counters should also provide less transistor count. However, most of the existing methods fail to provide less delay and average power [2-5]. Also, they fail to provide less transistor count. So, the development of a novel symmetric stacking based fast binary counters using modified gate diffusion input (M-GDI) technique [6] is required to provide less delay, average power, and transistor count. MGDI is a low-power design technique [6]. The MGDI technique allows the implementation of basic gates using two-three transistors. The proposed counter is designed using a stacker circuit, which reduces the number of gates required for the design. Due to this the delay decreases and the power consumed by the circuit also decreases. Thus, by designing the stacker-based counter using m-GDI technique the number of transistors decreases because the stacker circuit which used 3 input and gate and or gates are designed only by 4 transistors, where 8 transistors are required in CMOS logic. Thus, the count reduces, and the power consumed by the circuit also decreases. Thus, the proposed m-GDI based counter gives better performance than the traditional counters in terms of delay, the number of transistors, and power consumption. Simulations were run on the counters as well as the Wallace tree multiplier by using all the counters in 90nm technology. The same process is used to design counter-based Wallace tree multiplier [5,7], while the internal counters were changed. The paper is structured as follows. In section 2, MGDI technique for counters is introduced. Section 3 explains the stacker circuit for counters. Section 4 deals with the novel symmetric stacking based fast binary counters using MGDI technique. Section 5 deals with the novel fast binary counter-based Wallace tree multiplier. The simulation results are discussed in Section 6. Section 7 gives a conclusion. Symmetric Stacking Based Fast Binary Counter Using Modified Gate Diffusion Input (M-GDI) Technique Pavani Ivaturi, N. Prasad