energies Article Performance of Parallel Connected SiC MOSFETs under Short Circuits Conditions Ruizhu Wu 1 , Simon Mendy 1 , Nereus Agbo 1 , Jose Ortiz Gonzalez 1 , Saeed Jahdi 2 and Olayiwola Alatise 1, *   Citation: Wu, R.; Mendy, S.; Agbo, N.; Gonzalez, J.O.; Jahdi, S.; Alatise, O. Performance of Parallel Connected SiC MOSFETs under Short Circuits Conditions. Energies 2021, 14, 6834. https://doi.org/10.3390/en14206834 Academic Editor: Andrea Mariscotti Received: 21 September 2021 Accepted: 14 October 2021 Published: 19 October 2021 Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affil- iations. Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). 1 School of Engineering, University of Warwick, Coventry CV4 7AL, UK; robert.wu.1@warwick.ac.uk (R.W.); s.mendy@warwick.ac.uk (S.M.); nereus.agbo@warwick.ac.uk (N.A.); j.a.ortiz-gonzalez@warwick.ac.uk (J.O.G.) 2 Department of Electrical & Electronic Engineering, University of Bristol, Bristol BS8 1TH, UK; saeed.jahdi@bristol.ac.uk * Correspondence: o.alatise@warwick.ac.uk; Tel.: +44-(0)24-7655-1437 Abstract: This paper investigates the impact of parameter variation between parallel connected SiC MOSFETs on short circuit (SC) performance. SC tests are performed on parallel connected devices with different switching rates, junction temperatures and threshold voltages (V TH ). The results show that V TH variation is the most critical factor affecting reduced robustness of parallel devices under SC. The SC current conducted per device is shown to increase under parallel connection compared to single device measurements. V TH shift from bias–temperature–instability (BTI) is known to occur in SiC MOSFETs, hence this paper combines BTI and SC tests. The results show that a positive V GS stress on the gate before the SC measurement reduces the peak SC current by a magnitude that is proportional to V GS stress time. Repeating the measurements at elevated temperatures reduces the time dependency of the V TH shift, thereby indicating thermal acceleration of negative charge trapping. V TH recovery is also observed using SC measurements. Similar measurements are performed on Si IGBTs with no observable impact of V GS stress on SC measurements. In conclusion, a test methodology for investigating the impact of BTI on SC characteristics is presented along with key results showing the electrothermal dynamics of parallel devices under SC conditions. Keywords: bias temperature instability; SiC MOSFETs; short circuit measurements; threshold voltage shift 1. Introduction The ability of power devices to withstand short circuit currents is an important reliability metric. SiC MOSFETs, by virtue of a higher critical electric field, can block higher OFF-state voltages with reduced conduction losses while ON. This means SiC MOSFETs usually have smaller die size compared to comparatively rated silicon IGBTs. This smaller die size results in reduced switching losses due to smaller parasitic capacitances. However, this also means higher junction temperatures and smaller short circuit withstand times compared to silicon devices [1]. There are several papers that comprehend the performance and failure mechanisms of SiC MOSFETs under short circuit conditions, such as in [2–4]. In [5], the short circuit withstand time of 1.2 kV SiC MOSFETs was compared to that of 900 V silicon super-junction MOSFETs. The results showed higher performance in the SiC MOSFETs when energy density is used as a metric, however the SiC MOSFETs could not meet the 10 μs withstand time, unlike in the silicon devices. In [6], two failure mechanisms were identified in SiC MOSFETs under short circuits, namely, (i) parasitic BJT activation resulting from increased hole current flow in the MOSFET drift region and (ii) thermally induced degradation of the material and interfaces. The simulations showed significantly higher temperatures in the SiC MOSFET due to the smaller die size. In [7], the short circuit performance of 1.2 kV SiC Trench MOSFETs were investigated at low (400 V) and high (800 V) DC link voltages. The results at high V DC indicated thermal runaway as Energies 2021, 14, 6834. https://doi.org/10.3390/en14206834 https://www.mdpi.com/journal/energies