Asim M. Murshid and Faisal Bashir* Ground plane and selective buried oxide based planar junctionless transistor https://doi.org/10.1515/freq-2021-0059 Received March 9, 2021; accepted October 8, 2021; published online October 20, 2021 Abstract: In this work, we demonstrate a ground plane (GP) based Selective Buried Oxide (SELBOX) Junctionless Tran- sistor (JLT), named as GP-SELBOX-JLT. The use of GP and SELBOX in the proposed device reduces the electric field and enhances volume depletion in the channel, hence improves I ON /I OFF ratio and scalability. Using calibrated 2-D simulation, we have shown that proposed device exhibits better Short Channel Effect (SHE) immunity as compared to SOI-JLT. Therefore, the proposed GP-SELBOX-JLT can be scaled without degrading the performance in sub 20 nm regime. In addition, the ac study has shown that the cutoff frequency (f T ) of GP-SELBOX-JLT is almost equal to conventional SOI-JLT. Keywords: DIBL; gourd plane; junctionless; SELBOX; short channel effects (SCEs); SOI. 1 Introduction The important prerequisite for advanced Nano devices is the requirement of highly abrupt doping profiles at Source/ Channel and Drain/Channel interfaces [1–3]. However, this condition becomes stringent as the advanced device are scaled below 22/32 nm technology node, it is becomes very difficult to control such ultra-steep doping profiles. In this scenario, the devices without junction or Junctionless Transistors [3–6] are the potential candidates that can keep Moore’s law alive for some more time. The Junctionless transistors (JLT) consists of highly doped n type impurities along the device length (for n-Channel) and a high gate metal work function are used to control the charge carrier injection mechanism. Thus, JLT transistors are highly scalable and least complex due the absence of Source/ channel and Drain/channel junctions. However, the important requirement for JLT is the use extremely thin SOI film [7, 8] and high gate metal work function, greater than 5.5 eV to achieve full depletion across film in the vertical direction in the OFF condition (at zero gate voltage) [7]. The use extremely thin SOI substrate makes fabrication process difficult and costlier, while the use high gate metal work- function degrades the ON state performance. Recently new device architectures based on Junction- less concept has been proposed by different researchers. A high K material has been used for buried oxide and sub- strate is highly doped to get the better performance out the JLT [9], in other structure high metal work function is buried above buried to improve short channel effects [8] and bulk planar JLT uses diode isolation and BM-JLT used Schottky diode isolation to improve the performance [7, 10]. It has been suggested that JLT can be scaled below 10 nm node without facing issues like random dopant fluctuations and such devices have potential to compete with FinFET Technology [11, 12]. Besides this, conventional SOI-JLT cannot be used when the gate length is less than 32 nm technology node, due to higher susceptibility to short channel effects (SCEs) and increased leakage. In this paper, we try to address the above mentioned issues in conventional SOI-JLT using SELBOX and ground plane concept [13–18]. The proposed GP-SELBOX-JLT is a Junctionless device and a ground plane (GP) is placed in between the SELBOX, thus forms a type of PN structure in the vertical direction separated by thin intrinsic layer. The use of ground plane in between SELBOX aids the depletion on the bottom side of silicon film by using highly doped p-type (ground plane) doping impurity; therefore it helps to achieve full depletion of the carriers in the OFF state. Therefore, the use of SELBOX and Ground plane not only improves the scalability of the proposed device, but also keeps the proposed device cooler as compared to conven- tional SOI-JLT. Further, the ac analysis has revealed that the proposed device possesses f T and transconductance (g m ) at par with conventional SOI-JLT, but having higher f T as compared to other state of the art devices [7, 11] and has lower self-heating effect. Furthermore, the drain induced barrier lowering (DIBL) effect, I ON /I OFF ratio and threshold roll off has been improved by significant margin. *Corresponding author: Faisal Bashir, PhD, Department of Electronics and Insutrumentation technology, University of Kashmir, Srinagar, J&K, India, E-mail: faisalbashir4161@gmail.com. https://orcid.org/ 0000-0003-2473-2575 Asim M. Murshid, Software Department, College of Computer Science and Information Technology, University of Kirkuk, Kirkuk, Iraq, E-mail: asim.majeed2001@gmail.com. https://orcid.org/0000- 0003-0069-9432 Frequenz 2022; 76(1-2): 1–7