0167-9317/$ - see front matter Ó 2005 Published by Elsevier B.V. doi:10.1016/j.mee.2005.04.107 Microelectronic Engineering 80 (2005) 86–89 www.elsevier.com/locate/mee Effect of the dielectric thickness and the metal deposition technique on the mobility for HfO 2 /TaN NMOS devices L. Trojman 1, 3 , L.-Å. Ragnarsson 1 , L. Pantisano 1 , G.S. Lujan 1, 3 , M. Houssa 1 , T. Schram 1 , F. Cubaynes 2 , M. Schaekers 1 , A. Van Ammel 1 , G. Groeseneken 1, 3 , S. De Gendt 1, 4 and M. Heyns 1 1 IMEC, Kapeldreef 75, B-3001 Leuven, Belgium, Tel: +32-16-28-16-71, e-mail: Lionel.Trojman@imec.be 2 Philips Research Leuven, Kapeldreef 75, B-3001 Leuven, Belgium, 3 also at ESAT Department KU Leuven, Belgium, 4 also at Chemistry Department, KU Leuven, Belgium Abstract In this paper the effects from the high- dielectric thickness and the metal gate deposition technique on the mobility of n- channel MOS transistors are investigated. The results reveal mobility degradation due to an increase of charge density in the dielectric and / or at the material interfaces, not efficiently compensated by the screening effect from the gate. We correlate this mobility degradation to the reduction observed in a comparison between metal and poly-Si gated MOSFETs. It is shown that the mobility can be improved by using different metals deposition technique, which indicates that the mobility reduction is related to the deposition technique. Keywords: high- metal gate MOS transistor, mobility reduction, metal deposition, oxide thickness, screening effect 1. Introduction One of the greatest challenges in the high- device development is the metal gate integration. Although many deposition techniques can be considered, Atomic Layer Deposition (ALD) of the gate electrode is desirable for its conformality [1]. In this work we compare the electrical performance of devices with HfO 2 and TaN gates deposited either by ALD or PVD counting effect of the dielectric thickness. 2. Experimental N-channel MOSFETs were fabricated using a conventional gate flow, featuring either poly-Silicon (poly-Si) [2] or TaN [3] gate materials. Conventional SiON, SiON with a few monolayers of HfO 2 , or ALD HfO 2 grown on a chemical oxide (Imec clean) [4] were used as gate dielectrics. The TaN was either deposited by ALD [5] or sputtered by PVD. The FGA was done at 520ºC. The mobility extraction are carried out for V ds ~50mV, at several temperatures and corrected for series resistance effects by measuring on several gate lengths [6]. The inversion and depletion charge are measured by the split C-V.