Hindawi Publishing Corporation Journal of Electrical and Computer Engineering Volume 2011, Article ID 670508, 6 pages doi:10.1155/2011/670508 Research Article New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic Kirti Gupta, 1 Ranjana Sridhar, 1 Jaya Chaudhary, 1 Neeta Pandey, 1 and Maneesha Gupta 2 1 Electronics and Communication Department, Delhi Technological University, New Delhi, India 2 Electronics and Communication Division, Netaji Subhas Institute of Technology, New Delhi, India Correspondence should be addressed to Maneesha Gupta, maneesha gupta60@yahoo.co.in Received 31 March 2011; Revised 29 June 2011; Accepted 24 July 2011 Academic Editor: Mohamad Sawan Copyright © 2011 Kirti Gupta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits. 1. Introduction Nowadays, due to the remarkable growth in portable con- sumer electronics, the demand for low power and high speed computing circuits is on the rise. High speed micropro- cessors are the key elements used for data processing in these devices. An increase in the processor speed leads to an excessive power dissipation in portable devices which use batteries as the power sources. So, it is necessary to explore design techniques that reduce power consumption in such systems at high operating speeds. At the circuit level, the traditional CMOS logic style fails to simultaneously satisfy the speed and power requirements of these applications [1] and a different logic style is required [2–8]. Among the possible topologies, PFSCL is the most suit- able logic style for designing systems with optimum balance between speed and power dissipation [8–12]. A PFSCL style is derived from the single-ended source-coupled logic in which a positive feedback is introduced that significantly increases the speed as compared to traditional SCL circuits [8]. This improvement in speed can be traded off to reduce the power consumption of the circuits [9–11]. Thus, this logic style can be easily adopted in the design of high speed and high computing circuits for portable devices. In this paper, PFSCL has been used to develop different tristate circuits that are extensively used in high speed microprocessors and clock/data recovery systems to imple- ment multiplexers, phase detectors, and buses [13, 14]. Two different design techniques have been used to implement tristate circuits in PFSCL. The first one is a switched based technique while the second one uses the concept of sleep transistor. This paper is organized as follows. The architecture and the operation of PFSCL gates are described in Section 2. The design techniques to develop PFSCL-based tristate circuits are presented in Section 3. In the subsequent Section 4, the proposed tristate circuits are implemented and simulated using 0.18 μm CMOS technology parameters. Finally, the conclusions are drawn in the last section 2. PFSCL Circuits The basic circuit of a PFSCL inverter is shown in Figure 1. It consists of a source-coupled nMOS transistor pair, M1- M2 biased by the constant current source, I ss and a pMOS load transistor M3 [8–12]. The output of the gate is taken from the drain of pMOS active load, M3. A positive feedback is introduced in PFSCL by connecting the output of the gate to the input to transistor M2. This circuit works on the current steering principle. For a high input voltage V in , the bias current I ss is steered to M1 that produces a low