204 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 1, JANUARY 1999 Constant-Resistance Deep-Level Transient Spectroscopy in Si and Ge JFET’s Plamen V. Kolev, Member, IEEE, M. Jamal Deen, Senior Member, IEEE, James Kierstead, Member, IEEE, and Mauro Citterio, Member, IEEE Abstract— The recently introduced constant-resistance deep- level transient spectroscopy (CR-DLTS) was successfully applied to study virgin and radiation-damaged junction field-effect tran- sistors (JFET’s). We have studied three groups of devices: com- mercially available discrete silicon JFET’s; virgin and exposed to high-level neutron radiation silicon JFET’s, custom-made by using a monolithic technology; and commercially available dis- crete germanium p-channel JFET’s. CR-DLTS is similar to both the conductance DLTS and to the constant-capacitance variation (CC-DLTS). Unlike the conductance and current DLTS, it is inde- pendent of the transistor size and does not require simultaneous measurement of the transconductance or the free-carrier mobility for calculation of the trap concentration. Compared to the CC- DLTS, it measures only the traps inside the gate-controlled part of the space charge region. Comparisons have also been made with the CC-DLTS and standard capacitance DLTS. In addition, possibilities for defect profiling in the channel have been demonstrated. CR-DLTS was found to be a simple, very sensitive, and device area-independent technique which is well suited for measurement of a wide range of deep level concentrations in transistors. I. INTRODUCTION D EEP-LEVEL transient spectroscopy (DLTS) has been established as a major technique for investigating the properties of electrically active point defects responsible for creation of deep levels in the forbidden gap of semiconductors [1], [2]. However, a number of practical difficulties have limited the use of DLTS techniques for measurements of defects in field-effect transistors (FET’s). The standard capacitance DLTS technique [1] detects the thermal emission of trapped charges from the traps located in the depleted region of a p-n or Schottky diode as a change in the reverse-bias capacitance. This technique was applied later for measurements of MOS capacitors [3] and MOS transistors [4]. Because the relative change of the capacitance is proportional to the ratio of the trap concentration to the doping concentration, sensitive DLTS measurements can be performed on samples with relatively large area and capacitance. However, due to the continuing trend toward Manuscript received April 29, 1998. This work was supported in part by the Science Council of British Columbia, the Canadian Microelectronics Corporation, and the NSERC of Canada. The review of this paper was arranged by Editor J. N. Hollenhorst. P. V. Kolev and M. J. Deen are with the School of Engineering Science, Simon Fraser University, Vancouver, B.C., V5A 1S6, Canada (e-mail: ja- mal@cs.sfu.ca). J. Kierstead and M. Citterio are with the Brookhaven National Laboratory, Upton, NY 11973 USA (e-mail: kierstead@bnl.gov). Publisher Item Identifier S 0018-9383(99)00268-3. smaller devices, this requirement is a major limitation of the DLTS technique. To overcome this limitation for measurement of field effect transistors, two modifications of the DLTS technique were previously reported. In conductance DLTS [5], the effect of the charge emission of the trapped carriers on the threshold voltage is indirectly monitored by measuring the change in the small-signal ac channel conductance by an RCL meter. For calculation of the trap concentration, the surface free carrier mobility was assumed constant over the entire measured temperature range, and this is a very rough approximation. In a later modification [6], capacitance–voltage – measurements were used to calibrate a theoretical characterization model and to obtain the needed parameters for the calculation of the trap concentration. Measurement of the drain current transient at a constant gate bias is another technique for indirect observation of the changes in the threshold voltage [7]. Compared to the small-signal ac conductance DLTS [5], this method requires simpler instrumentation and has the potential to measure higher emission rates; but this is at the expense of decreased sensitivity because of the missing phase-sensitive-detection technique employed in the RCL meter. In addition, the change of the FET transconductance in the entire temperature range must be monitored to determine the trap concentration. Later [8], was modeled by directly calculating the transient of the charge in the inversion layer, accounting for mobility field-effect dependence and series resistance effect, and replac- ing temperature scanning by measurements at several fixed temperatures. One recent variation of the DLTS technique [9] is based on direct measurement of the changes in the threshold volt- age. This technique is called constant-resistance (CR-)DLTS and was demonstrated with measurements of deep-submicron enhancement mode MOSFET’s [9], [10] and buried-channel depletion mode MOSFET’s [11]. This technique should be useful for measurement of any FET’s where the charge emis- sion from the traps can affect the source-drain conductance and the resulting conductance change can be compensated by adjusting the gate voltage. In this work, we explore the application of CR-DLTS in determining the trap characteristics of junction field-effect transistors (JFET’s), and compare the new technique with the constant-capacitance and standard capacitance DLTS. Despite the early discovery of the JFET by Shockley in 1952 [12] and its demonstration one year later [13], this 0018–9383/99$10.00  1999 IEEE