Analog Integrated Circuits and Signal Processing, 15, 227–237 (1998) c  1998 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. A 16 × 16 Cellular Neural Network Universal Chip: The First Complete Single-Chip Dynamic Computer Array with Distributed Memory and with Gray-Scale Input-Output J. M. CRUZ 1 AND L. O. CHUA 2 1 Department of Electrical Engineering and Computer Sciences, University of California, Berkeley; Current address: Sun Microsystems, Inc. 2 Department of Electrical Engineering and Computer Sciences, University of California, Berkeley Abstract. This paper presents a 16 × 16 Cellular Neural Network Universal Chip with analog input and output ports, which can read in and process gray-scale images in the analog domain. The chip contains about 5,000 analog multipliers and has been fabricated in a 0.8 μm CMOS process. Key Words: CNN, CNN universal chip, computer array, CMOS, analog, nonlinear dynamics 1. Introduction The Cellular Neural Network (CNN) architecture was presented in [1] and [2]. This architecture allows par- allel analog processing of images using an array of locally interconnected cells with fixed weights. The local interconnection feature allows efficient VLSI im- plementations [3][4], and many CNN chips have been reported since the first operational CNN chip was pre- sented in 1991 [5]. In 1993 the CNN architecture was augmented, in- corporating programmable weights, local storage, and local logic. The new augmented architecture is called Cellular Neural Network Universal Machine [6], as it has proven to be able to solve all the algorithms that can be executed by a Turing Machine [7]. Different types of chip implementations of the CNN Universal Machine or parts of it have been reported recently [8]–[12], and they are usually referred to as CNN Universal Chips. These implementations in- clude: (a) designs which operate according to the orig- inal CNN continuous-time analog-amplitude dynam- ical equations given in [1], as in the design reported in [12] and in a programmable chip design without logic memory reported in [11]; (b) a design which op- erates according to a modified continuous-time analog- amplitude CNN equation in which the state variable is clipped to unity and the final chip output is binary [8]; (c) a design which emulates the CNN dynamics by using discrete time samples but maintaining analog- amplitude [9]; and (d) a digital implementation which emulates the original CNN dynamics by using discrete time samples and discrete amplitude values [10]. These implementations vary in their area and speed efficiency, with reported data showing higher efficiency in both respects for circuits implementing the CNN dynamics directly in the analog domain. These reported chips also vary in other aspects of their functionality, includ- ing their capability to locally store and logically ma- nipulate binary images, and their capability to input, store, process, and output not only binary images but gray-scale images. In this paper we present the first CNN Universal Chip with the capability to input, store, process, and output gray-scale images in the analog domain combined with the capability to locally store and logically process bi- nary images. The chip has been fabricated in a 0.8um 3-metal 1-poly technology of HP. Each cell implements the dynamics of the CNN equation with a state resistance by state capacitance product below 90 ns. For typical applications the dy- namics of the entire array settles to a constant state in 200 to 250 ns. Each cell has a computing power, ex- cluding input-output operations, of 4 to 5 million pixels per second and the entire chip has a peak computing capability of 1 billion pixels per second. The maxi- mum electrical power consumption of the entire chip when operating at 5 Volts is 0.3 Watts. 2. Chip Architecture Figure 1 shows a photograph of the chip, packaged in a 132 PGA. The main components of the chip are as follows. 3