561 | Page Gate All Around FET: An Alternative of FinFET for Future Technology Nodes Chander Mohan 1 , Sumit Choudhary 2 , B. Prasad 3 1,2,3 Department of Electronic Science, Kurukshetra University, Kurukshetra, Haryana, (India) ABSTRACT Scaling of devices is reaching a brick wall because of short channel effects and quantum behavior of carriers at this scaled level. At this level, the quantum mechanics became more commanding over classical mechanics. To keep Moore’s law alive, Gate All Around FET is a better candidate over Fin FET and other existing sub 22 nm device architectures because of its gate coupling which tunes the channel more precisely and accurately. In GAA device architecture the SCE are minimized as compared to FinFET at same technology node. Physical device models ofquantum level and theircalibrated parameters usedto simulate devices below 14nm technology were discussed. In this paper the transfer characteristics, output characteristics, gain, mobility roll off, subthreshold slope, I ON /IOFF ratio and DIBL of GAAFET simulated. Also compared these SCE in squared channel GAA and Cylindrical Channel GAA Structures. Simulated result shows that the SCEs were significantly reduced in cylindrical GAAFET. DIBL and SS were found to be 78mV/dec and 71mV/V vs. 113mV/dec and 73mV/V in Cylindrical GAAFET, Square channel GAAFET respectively. Keywords: ATLAS, FinFET, Gate All Around (GAA), Scaling, Short Channel Effects (SCEs). I. INTRODUCTION From past half century, Transistor is being continuously proven to be the most significant invention of engineering and is the backbone of every field. The secret to this much success lies in the fact that Transistor has followed a constant miniaturization trend initially predicted by G. Moore [1]. While it was a standard to have a feature size of 10 um in early days of MOSFETdevelopment [2], now the same is nearly 10 nm, and efforts are continuously made to shrink it more. This trend has allowed semiconductor industry to provide more and more features with reduced cost and power consumption. But, scaling has its own limitations, which further became more significant and challenging to rectify for feature size in Nanometer regime [3]. Device with feature sizesbelow 100 nm range suffers fromlateral SCEs such as dopant fluctuation, hot electron effect, carrier velocity saturation, drain induced barrier lowering (DIBL). Subthreshold Swing (SS), leakage current, etc. and vertical gate insulator tunneling[4] [5] [6] [7]. Due to fundamental physical limitations, the scaling of planer MOSFET was predicted to be limited to 15nm, butit has already ended with 32nm technology node due to difficulties in maintaining the gate coupling of device with planer structure.To minimise SCEs and to improve the device performance changes such as strained Silicon, Silicon on Insulator (SOI), high k insulator (HK), metal gate (MG), non-uniform doping, [8] [9] [10] [11] [12][13]has been suggested and utilised in device design.But, to maintain suitable electrostatic gate control over channel these innovations were not sufficient and many non-planer device architectures like Dual gate, Pi- gate, Omega Gate, FinFET/Tri-Gate were also proposed and investigated [14] [15] [16] [17]. But due to its